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HLX6228ASN Datasheet(PDF) 8 Page - List of Unclassifed Manufacturers |
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HLX6228ASN Datasheet(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 12 page  HLX6228 8 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycle The RAM is asynchronous in operation, allowing the read cycle to be controlled only by chip select (NCS) (refer to Read Cycle timing diagram). To perform a valid read opera- tion, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output drivers can be controlled independently by the NOE signal. To control a read cycle with NCS, all addresses and CE must be valid prior to or coincident with the enabling NCS edge transition delayed. Read control with NCS requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The device must be controlled in this fashion to meet the timing specifications herein. The data output will not become valid until TSLQV time following return of NCS to a low state. Data outputs will enter a high impedence state TSHQZ time following a disabling NCS edge transition. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by only chip select (NCS) (refer to Write Cycle timing diagrams). To perform a write operation, both NWE and NCS must be low, and CE must be high. This part must be Write controlled using the NCS pin; it requires that NCS returns to a high state for at least 5ns whenever there is an address change. This 5ns pulse to high provides the part with a defined pre-charge pulse duration to ensure that the new address is latched. The part must be controlled in this fashion to meet the timing specifications defined. Both CE and NCS fully dis- able the RAM decode logic and input buffers for power savings. To write data into the RAM, NWE and NCS must be held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecu- tive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/ TAVSH/TAVEL also must be provided for during the write operation. Hold times for address inputs and data inputs with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV. |
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