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X24257Z-2.5 Datasheet(PDF) 5 Page - Xicor Inc. |
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X24257Z-2.5 Datasheet(HTML) 5 Page - Xicor Inc. |
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5 / 19 page  X24257 – Preliminary Information Characteristics subject to change without notice. 5 of 19 REV 1.1.1 10/15/00 www.xicor.com WRITE OPERATIONS Byte Write For a write operation, the device follows “3 byte” proto- col, consisting of one Slave Address Byte, one Word Address Byte 1, and the Word Address Byte 0, which gives the master access to any one of the words in the array. Upon receipt of the Word Address Byte 0, the device responds with an acknowledge, and waits for the first eight bits of data. After receiving the 8 bits of the data byte, the device again responds with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the device begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the device inputs are disabled and the device will not respond to any requests from the master. The SDA pin is at high impedance. See Figure 5. Page Write The device is capable of a 64 byte page write operation. It is initiated in the same manner as the byte write operation; but instead of terminating the write operation after the first data word is transferred, the master can transmit up to sixty-three more words. The device will respond with an acknowledge after the receipt of each word, and then the byte address is internally incre- mented by one. The page address remains constant. When the counter reaches the end of the page, it “rolls over” and goes back to the first byte of the current page. This means that the master can write 64-bytes to the page beginning at any byte. If the master begins writing at byte 32, and loads 64-bytes, then the first 32-bytes are written to bytes 32 through 63, and the last 16 words are written to bytes 0 through 31. After- wards, the address counter would point to byte 32. If the master writes more than 64 bytes, then the previously loaded data is overwritten by the new data, one byte at a time. The master terminates the data byte loading by issuing a stop condition, which causes the device to begin the nonvolatile write cycle. As with the byte write operation, all inputs are disabled until completion of the internal write cycle. Refer to Figure 6 for the address, acknowl- edge, and data transfer sequence. Figure 5. Byte Write Sequence Figure 6. Page Write Sequence Signals from the Master SDA Bus Signals from the Slave S T A R T Slave Address S T O P A C K A C K A C K A C K Byte 1 Data 1 0 1 0 0 Word Address Byte 0 S P 0 Word Address S1S0 S T A R T S T O P A C K A C K A C K A C K A C K Data (0) (n) 0 S P Data 1 0 1 0 (0 ≤ n ≤ 64) Signals from the Master SDA Bus Signals from the Slave Slave Address Byte 1 Word Address Byte 0 Word Address 0 S1S0 |
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