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AZ100EL11TR1 Datasheet(PDF) 1 Page - List of Unclassifed Manufacturers |
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1 / 6 page AZ10EL11 AZ100EL11 ECL/PECL 1:2 Differential Fanout Buffer 1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541 www.azmicrotek.com ARIZONA MICROTEK, INC. FEATURES • 265ps Propagation Delay • 5ps Skew Between Outputs • High Bandwidth Output Transitions • 75k Ω Internal Input Pulldown Resistors • Direct Replacement for ON Semiconductor MC10EL11 & MC100EL11 DESCRIPTION The AZ10/100EL11 is a differential 1:2 fanout gate. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the EL11 is ideally suited for those applications that require the ultimate in AC performance. The differential inputs of the EL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to VEE) the Q outputs will go LOW. NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established. LOGIC DIAGRAM AND PINOUT ASSIGNMENT PACKAGE AVAILABILITY PACKAGE PART NO. MARKING SOIC 8 AZ10EL11D AZM10EL11 SOIC 8 T&R AZ10EL11DR1 AZM10EL11 SOIC 8 T&R AZ10EL11DR2 AZM10EL11 SOIC 8 AZ100EL11D AZM100EL11 SOIC 8 T&R AZ100EL11DR1 AZM100EL11 SOIC 8 T&R AZ100EL11DR2 AZM100EL11 TSSOP 8 AZ10EL11T AZTEL11 TSSOP 8 T&R AZ10EL11TR1 AZTEL11 TSSOP 8 T&R AZ10EL11TR2 AZTEL11 TSSOP 8 AZ100EL11T AZHEL11 TSSOP 8 T&R AZ100EL11TR1 AZHEL11 TSSOP 8 T&R AZ100EL11TR2 AZHEL11 PIN DESCRIPTION PIN FUNCTION D, D ¯ Data Inputs Q0, Q0 ¯¯ , Q1, Q1 ¯¯ Data Outputs VCC Positive Supply VEE Negative Supply 8 5 6 7 4 3 2 1 VCC D VEE Q0 Q0 Q1 Q1 D |
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