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CS61582-IQ5 Datasheet(PDF) 6 Page - Cirrus Logic

Part No. CS61582-IQ5
Description  DUAL T1/E1 LINE INTERFACE
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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 6 page
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SWITCHING CHARACTERISTICS - T1 CLOCK/DATA (TA = -40 to 85 °C; power supply
pins within
±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter
Symbol
Min
Typ
Max
Units
TCLK Frequency
(Note 25)
ftclk
-
1.544
-
MHz
TCLK Duty Cycle
tpwh2/tpw2
30
50
70
%
RCLK Duty Cycle
tpwh1/tpw1
45
50
55
%
Rise Time (All Digital Outputs)
(Note 26)
tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 26)
tf
-
-
65
ns
RPOS/RNEG to RCLK Rising Setup Time
tsu1
-
274
-
ns
RCLK Rising to RPOS/RNEG Hold Time
th1
-
274
-
ns
TPOS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG Hold Time
th2
25
-
-
ns
Notes: 25. The maximum burst rate of a gapped TCLK input clock is 8.192 MHz. The maximum gap size
that can be tolerated on TCLK is 28 UIp-p.
26. At max load of 50 pF.
SWITCHING CHARACTERISTICS - E1 CLOCK/DATA (TA = -40 to 85 °C; power supply
pins within
±5% of nominal; Inputs: Logic 0 = 0V, Logic 1 = DV+) (See Figures 1, 2, and 3)
Parameter
Symbol
Min
Typ
Max
Units
TCLK Frequency
(Note 25)
ftclk
-
2.048
-
MHz
TCLK Duty Cycle
tpwh2/tpw2
30
50
70
%
RCLK Duty Cycle
tpwh1/tpw1
45
50
55
%
Rise Time (All Digital Outputs)
(Note 26)
tr
-
-
65
ns
Fall Time (All Digital Outputs)
(Note 26)
tf
-
-
65
ns
RPOS/RNEG to RCLK Rising Setup Time
tsu1
-
194
-
ns
RCLK Rising to RPOS/RNEG Hold Time
th1
-
194
-
ns
TPOS/TNEG to TCLK Falling Setup Time
tsu2
25
-
-
ns
TCLK Falling to TPOS/TNEG Hold Time
th2
25
-
-
ns
6
DS224PP1




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