CY2283
PRELIMINARY
3
CPU and PCI Clock Driver Strengths
• Matched impedances on both rising and falling edges on
the output drivers
• Output impedance: 25
Ω (typical) measured at 1.5V
Serial Configuration Map
• The Serial bits will be read by the clock driver in the following
order:
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
.
.
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
• Reserved and unused bits should be programmed to “0”.
•I2C Address for the CY2283 is:
Actual Clock Frequency Values
Clock Output
Target
Frequency
(MHz)
Actual
Frequency
(MHz)
PPM
CPUCLK
66.67
66.51
–2346
CPUCLK
75.0
75.0
0
CPUCLK
83.33
83.14
-2346
CPUCLK
100.0
99.77
-2346
USBCLK
48.0
48.01
167
Power Management Logic[4] - Active when MODE pin is held ‘LOW’
CPU_STOP
PCI_STOP
PWR_DWN
CPUCLK
PCICLK
PCICLK_F
Other
Clocks
Osc.
PLLs
X
X
0
Low
Low
Stopped
Stopped
Off
Off
0
0
1
Low
Low
Running
Running
Running
Running
0
1
1
Low
33/30 MHz
Running
Running
Running
Running
1
0
1
66/75/83/100MHz
Low
Running
Running
Running
Running
1
1
1
66/75/83/100MHz
30/33.3 MHz
Running
Running
Running
Running
A6
A5
A4
A3
A2
A1
A0
R/W
1101001
----
Byte 0: Functional and Frequency Select Clock
Register (1 = Enable, 0 = Disable)
Bit
Pin #
Description
Bit 7
--
(Reserved) drive to ‘0’
Bit 6
--
(Reserved) drive to ‘0’
Bit 5
--
(Reserved) drive to ‘0’
Bit 4
--
(Reserved) drive to ‘0’
Bit 3
--
(Reserved) drive to ‘0’
Bit 2
--
(Reserved) drive to ‘0’
Bit 1
Bit 0
--
Bit 1
1
1
0
0
Bit 0
1 - Three-State
0 - N/A
1 - Testmode
0 - Normal Operation
Select Functions
Functional Description
Outputs
CPU
PCI, PCI_F
SDRAM
Ref
IOAPIC
USBCLK
AGP
Three-State
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Test Mode[6]
TCLK/2[5]
TCLK/4
TCLK/2
TCLK
TCLK
TCLK/2
TCLK/2
Notes:
4.
AGP clocks are free-running and stop only when the PWR_DWN pin is asserted. The frequency of the AGP clocks is as shown in the Function Table.
5.
TCLK supplied on the XTALIN pin in Test Mode.
6.
Valid only for SEL1=0.
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