CY7C09159
CY7C09169
PRELIMINARY
4
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65
°C to +150°C
Ambient Temperature with Power Applied ..–55
°C to +125°C
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State ................................. –0.5V to +7.0V
DC Input Voltage............................................ –0.5V to +7.0V
Output Current into Outputs (LOW) ............................. 20 mA
Static Discharge Voltage ........................................... >2001V
Latch-Up Current ..................................................... >200 mA
Selection Guide
CY7C09159
CY7C09169
-6
CY7C09159
CY7C09169
-7
CY7C09159
CY7C09169
-12
fMAX2 (MHz) (Pipelined)
100
83
50
Max Access Time (ns) (Clock to Data, Pipelined)
6.5
7.5
12
Typical Operating Current ICC (mA)
250
235
195
Typical Standby Current for ISB1 (mA)
(Both Ports TTL Level)
45
40
30
Typical Standby Current for ISB3 (mA)
(Both Ports CMOS Level)
0.05
0.05
0.05
Pin Definitions
Left Port
Right Port
Description
A0L–A13L
A0R–A13R
Address Inputs. (A0−A12 for 8K; A0−A13 for 16K devices)
ADSL
ADSR
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW during
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
CE0L,CE1L
CE0R,CE1R
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted to
their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKL
CLKR
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENL
CNTENR
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted
LOW.
CNTRSTL
CNTRSTR
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disabled by asserting ADS or CNTEN.
I/O0L–I/O8L
I/O0R–I/O8R
Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 devices).
OEL
OER
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read
operations.
R/WL
R/WR
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array. For
read operations, assert this pin HIGH.
FT/PIPEL
FT/PIPER
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW. For
pipelined mode operation, assert this pin HIGH.
GND
Ground Input.
NC
No Connect.
VCC
Power Input.
Operating Range
Range
Ambient
Temperature
VCC
Commercial
0
°C to +70°C
5V
± 10%
Industrial
−40
°C to +85°C
5V
± 10%
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