Ver 3.2

Dec 13, 2004

TEL: 886-3-5788833

http://www.gmt.com.tw

3

G261

Global Mixed-mode Technology Inc.

Application Information

Figure 1. LVD SCSI Discrete Resistor Stack

Table1. Resistor Network v.s Standard

OUTPUTS

SPECIFICATION

112.9mV Diff Bias

100mV to 125mV

1.25V Common Mode

1.2V to 1.30V

Application Note: The resistor network, along with the 1.75V and 0.75V references will give the correct dif-

ferential impedance, bias voltage, common mode impedance and common mode voltage as show in Table

1.

Layout guideline:

1. For stable operation, the 1µF capacitor on TERMPWR pin and 4.7µF capacitors on REG1 and REG2

pins must be placed within 0.25 inch of their respective pins.

2. The PCB trace length form Lx- and Lx+ to the connector pins (all 27pairs) must be of equal length, in or-

der to minimize the signal skew among these pairs. In addition, these traces must be as short as possible,

in order to minimize capacitance.

REF

1.3V

SOURCE/SINK REGULATOR

50 mA SOURCE/SINK

TERMPWR

50 mA SOURCE/SINK

DIFFSENSE

REG1

REG2

SOURCE 5 to 15mA

REF

1.75V

REF

0.75V

SOURCE/SINK REGULATOR

4.7µF

4.7µF

121 1%

121 1%

L1-

L1+

L27-

L27+

475 1%

475 1%

475 1%

PGND

475 1%

1.3V ±0.1V

1.75V ±50mV

0.75V ±50mV

1µF

DIFFSENSE: SOURCE ONLY

FROM TERMPWR

to DIFFSENS pin

REF

1.3V

SOURCE/SINK REGULATOR

50 mA SOURCE/SINK

TERMPWR

50 mA SOURCE/SINK

DIFFSENSE

REG1

REG2

SOURCE 5 to 15mA

REF

1.75V

REF

0.75V

SOURCE/SINK REGULATOR

4.7µF

4.7µF

121 1%

121 1%

L1-

L1+

L27-

L27+

475 1%

475 1%

475 1%

PGND

475 1%

1.3V ±0.1V

1.75V ±50mV

0.75V ±50mV

1µF

DIFFSENSE: SOURCE ONLY

FROM TERMPWR

to DIFFSENS pin