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LH7A400N0B000 Datasheet(PDF) 6 Page - Sharp Corporation |
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LH7A400N0B000 Datasheet(HTML) 6 Page - Sharp Corporation |
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6 / 53 page  LH7A400 32-Bit System-on-Chip 6 12/8/03 Preliminary Data Sheet M13 L15 A2/SA0 • Asynchronous Address Bus • Synchronous Address Bus LOW LOW 12 mA K16 K12 A3/SA1 LOW LOW 12 mA K15 K13 A4/SA2 LOW LOW 12 mA K14 K16 A5/SA3 LOW LOW 12 mA J8 J13 A6/SA4 LOW LOW 12 mA J16 J11 A7/SA5 LOW LOW 12 mA J14 J16 A8/SA6 LOW LOW 12 mA J9 H15 A9/SA7 LOW LOW 12 mA H16 H10 A10/SA8 LOW LOW 12 mA H14 H12 A11/SA9 LOW LOW 12 mA G16 G15 A12/SA10 LOW LOW 12 mA G14 G10 A13/SA11 LOW LOW 12 mA G13 G11 A14/SA12 LOW LOW 12 mA F16 F16 A15/SA13 LOW LOW 12 mA F14 E16 A16/SB0 • Asynchronous Address Bus • Synchronous Device Bank Address 0 LOW LOW 12 mA E16 F13 A17/SB1 • Asynchronous Address Bus • Synchronous Device Bank Address 1 LOW LOW 12 mA E13 E14 A18 Asynchronous Address Bus LOW LOW 12 mA F11 D15 A19 D15 C16 A20 C16 C15 A21 B16 C14 A22 A15 B15 A23 A13 E11 A24 G8 D8 A25/SCIO • Asynchronous Memory Address Bus • Smart Card Interface I/O (Data) LOW: A25 LOW 12 mA F8 B7 A26/SCCLK • Asynchronous Memory Address Bus • Smart Card Interface Clock LOW: A26 LOW 12 mA A8 A7 A27/SCRST • Asynchronous Memory Address Bus • Smart Card Interface Reset LOW: A27 LOW 12 mA D8 C8 nOE Asynchronous Memory Output Enable HIGH HIGH 12 mA C8 F8 nWE0 Asynchronous Memory Write Byte Enable 0 HIGH HIGH 12 mA D10 D9 nWE3 Asynchronous Memory Write Byte Enable 3 HIGH HIGH 8 mA B10 E9 CS6/SCKE1_2 • Asynchronous Memory Chip Select 6 • Synchronous Memory Clock Enable 1 OR 2 LOW: CS6 LOW 12 mA C10 A10 CS7/SCKE0 • Asynchronous Memory Chip Select 7 • Synchronous Memory Clock Enable 0 LOW: CS7 LOW 12 mA G9 A11 SCKE3 Synchronous Memory Clock Enable 3 LOW LOW 12 mA A10 B10 SCLK Synchronous Memory Clock LOW LOW 20 mA (sink) 12 mA (source) C14 C13 nSCS0 Synchronous Memory Chip Select 0 HIGH HIGH 12 mA D13 A15 nSCS1 Synchronous Memory Chip Select 1 HIGH HIGH 12 mA E11 D11 nSCS2 Synchronous Memory Chip Select 2 HIGH HIGH 12 mA A12 E10 nSCS3 Synchronous Memory Chip Select 3 HIGH HIGH 12 mA C12 A13 nSWE Synchronous Memory Write Enable HIGH HIGH 12 mA C11 B11 nCAS Synchronous Memory Column Address Strobe Signal HIGH HIGH 12 mA Table 1. Functional Pin List (Cont’d) PBGA PIN CABGA PIN SIGNAL DESCRIPTION RESET STATE STANDBY STATE OUTPUT DRIVE |
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