M5M29GB640C3BXAI-12 datasheet(4/42 Pages) ETC

Part #	M5M29GB640C3BXAI-12

Description	3.3V ONLY FLASHMEMORY

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P/N:PM0900

M5M29GB640VP

REV. 0.3, NOV. 21, 2002

Table 1. Pin Description

Symbol

Type

Description and Function

A0-A21

input

Address inputs for memory address. Data pin float to high-impedance when the chip is

deselected or outputs are disable. Addresses are internally latched during a write or

erase cycle.

DQ0-DQ15

input/output

Data inputs/outputs: Inputs array data on the second CE and WE cycle during a pro-

gram command. Data is internally latched. Outputs array and configuration data. The

data pin float to tri-state when the chip is de-selected.

CE

input

Activates the device's control logic, input buffers, and sense amplifiers. CE high de-

selects the memory device and reduce power consumption to standby level. CE is

active low.

RP

input

Reset Deep Power Down: when RP=VIL, the device is in reset/deep power down mode,

which drives the outputs to High Z, resets the WSM and minimizes current level.

When RP=VIH, the device is normal operation. When RP transition the device defaults

to the read array mode.

WE

input

Write Enable: to control write to CUI and array sector. WR=VIL becomes active. The

data and address is latched WE on the rising edge of the second WE pulse.

OE

input

Output enable: gates the device's outputs during a real cycle.

WP

input

Write protect: when WP is VIL, the boot sectors cannot be written or erased. When WP

is VIH, locked boot sectors cannot be written or erase. WP is not affected parameter

and main sectors.

VCC

supply

Device power supply: (2.7V~3.6V).

VCCQ

input

I/O Power Supply: supplies for input/output buffers. (Refer to section 6.2.6)

GND

supply

Ground voltage: all the GND pin shall not be connected.

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M5M29GB640C3BXAI-12 Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers

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