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MC68HC11A1CFN2 Datasheet(PDF) 6 Page - Motorola, Inc |
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MC68HC11A1CFN2 Datasheet(HTML) 6 Page - Motorola, Inc |
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6 / 158 page  MOTOROLA MC68HC11A8 vi TECHNICAL DATA 9.1.2.6 Pulse Accumulator .................................................................... 9-4 9.1.2.7 COP .......................................................................................... 9-4 9.1.2.8 SCI Serial l/O ............................................................................ 9-4 9.1.2.9 SPI Serial l/O ............................................................................. 9-4 9.1.2.10 A/D Converter ........................................................................... 9-4 9.1.2.11 System ...................................................................................... 9-4 9.1.3 Computer Operating Properly (COP) Reset ...................................... 9-5 9.1.4 Clock Monitor Reset .......................................................................... 9-6 9.1.5 Configuration Options Register (OPTION) ........................................ 9-6 9.2 Interrupts ................................................................................................... 9-7 9.2.1 Software Interrupt (SWI) .................................................................... 9-9 9.2.2 Illegal Opcode Trap ........................................................................... 9-9 9.2.3 Interrupt Mask Bits in Condition Code Register ................................ 9-9 9.2.4 Priority Structure .............................................................................. 9-10 9.2.5 Highest Priority I Interrupt Register (HPRIO) .................................. 9-10 9.3 Low-Power Modes ................................................................................... 9-17 9.3.1 WAIT Instruction .............................................................................. 9-17 9.3.2 STOP Instruction ............................................................................. 9-17 10 CPU, ADDRESSING MODES, AND INSTRUCTION SET 10.1 CPU Registers ......................................................................................... 10-1 10.1.1 Accumulators A and B ..................................................................... 10-1 10.1.2 Index Register X (IX) ....................................................................... 10-1 10.1.3 Index Register Y (IY) ....................................................................... 10-2 10.1.4 Stack Pointer (SP) ........................................................................... 10-2 10.1.5 Program Counter (PC) .................................................................... 10-2 10.1.6 Condition Code Register (CCR) ...................................................... 10-2 10.1.6.1 Carry/Borrow (C) ..................................................................... 10-3 10.1.6.2 Overflow (V) ............................................................................ 10-3 10.1.6.3 Zero (Z) ................................................................................... 10-3 10.1.6.4 Negative (N) ............................................................................ 10-3 10.1.6.5 Interrupt Mask (I) ..................................................................... 10-3 10.1.6.6 Half Carry (H) .......................................................................... 10-3 10.1.6.7 X Interrupt Mask (X) ................................................................ 10-3 10.1.6.8 Stop Disable (S) ...................................................................... 10-3 10.2 Addressing Modes ................................................................................... 10-3 10.2.1 Immediate Addressing ..................................................................... 10-4 10.2.2 Direct Addressing ............................................................................ 10-4 10.2.3 Extended Addressing ...................................................................... 10-4 10.2.4 Indexed Addressing ......................................................................... 10-4 10.2.5 Inherent Addressing ........................................................................ 10-4 10.2.6 Relative Addressing ........................................................................ 10-4 10.2.7 Prebyte ............................................................................................ 10-5 10.3 Instruction Set ......................................................................................... 10-5 A ELECTRICAL CHARACTERISTICS |
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