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MC68HC11A0CP2 Datasheet(PDF) 9 Page - Motorola, Inc |
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MC68HC11A0CP2 Datasheet(HTML) 9 Page - Motorola, Inc |
9 / 158 page MC68HC11A8 MOTOROLA TECHNICAL DATA ix LIST OF ILLUSTRATIONS Figure Page 1-1 Block Diagram ................................................................................................ 1-2 1-2 Programming Model ....................................................................................... 1-3 2-1 Common Crystal Connections ........................................................................ 2-2 2-2 External Oscillator Connections ..................................................................... 2-2 2-3 One Crystal Driving Two MCUs ..................................................................... 2-2 2-4 Address/Data Demultiplexing ......................................................................... 2-8 3-1 Memory Maps ................................................................................................. 3-1 5-1 Data Format ................................................................................................... 5-2 5-2 Sampling Technique Used on All Bits ............................................................ 5-3 5-3 Examples of Start Bit Sampling Techniques .................................................. 5-4 5-4 SCI Artificial Start Following a Framing Error ................................................. 5-4 5-5 SCI Start Bit Following a Break ...................................................................... 5-4 5-6 Serial Communications Interface Block Diagram ........................................... 5-7 5-7 Rate Generator Division ............................................................................... 5-12 6-1 Data Clock Timing Diagram ........................................................................... 6-2 6-2 Serial Peripheral Interface Block Diagram ..................................................... 6-3 6-3 Serial Peripheral Interface Master-Slave Interconnection .............................. 6-4 7-1 A/D Conversion Sequence ............................................................................. 7-2 7-2 A/D Pin Model ................................................................................................ 7-2 9-1 Reset Timing .................................................................................................. 9-2 9-2 Simple LVI Reset Circuit ................................................................................ 9-3 9-3 Interrupt Stacking Order ................................................................................. 9-9 9-4 Processing Flow Out of Resets (Sheet 1 of 2) ............................................. 9-12 9-4 Processing Flow Out of Resets (Sheet 2 of 2) ............................................. 9-13 9-5 Interrupt Priority Resolution (Sheet 1 of 2) ................................................... 9-14 9-5 Interrupt Priority Resolution (Sheet 2 of 2) ................................................... 9-15 9-6 Interrupt Source Resolution Within SCI ........................................................ 9-16 10-1 Programming Model ..................................................................................... 10-2 10-2 Special Operations ..................................................................................... 10-12 A-1 Test Methods .................................................................................................. A-4 A-2 Timer Inputs ................................................................................................... A-7 A-3 POR and External Reset Timing Diagram ...................................................... A-8 A-4 STOP Recovery Timing Diagram ................................................................... A-9 A-5 WAIT Recovery Timing Diagram .................................................................. A-10 A-6 Interrupt Timing Diagram .............................................................................. A-11 A-7 Port Write Timing Diagram ........................................................................... A-14 A-8 Port Read Timing Diagram ........................................................................... A-14 A-9 Simple Output Strobe Timing Diagram ......................................................... A-14 A-10 Simple Input Strobe Timing Diagram ........................................................... A-15 A-11 Port C Input Handshake Timing Diagram ..................................................... A-15 A-12 Port C Output Handshake Timing Diagram .................................................. A-15 A-13 Three-State Variation of Output Handshake Timing Diagram (STRA Enables Output Buffer) A-16 A-14 Multiplexed Expansion Bus Timing Diagram ................................................ A-21 A-8 a) SPI Master Timing (CPHA = 0) ................................................................ A-24 |
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