256MB / 512MB (x64)

168-PIN SDRAM DIMMs

32,64 Meg x 64 SDRAM DIMMs

Micron Technology, Inc., reserves the right to change products or specifications without notice.

SD8_16C32_64x64AG_C.fm - Rev. C 11/02

8

©2002, Micron Technology Inc.

MAND INHIBIT or NOP. Starting at some point during

this 100µs period and continuing at least through the

end of this period, COMMAND INHIBIT or NOP com-

mands should be applied.

Once the 100µs delay has been satisfied with at least

one COMMAND INHIBIT or NOP command having

been applied, a PRECHARGE command should be

applied. All device banks must then be precharged,

thereby placing the device in the all banks idle state.

Once in the idle state, two AUTO REFRESH cycles

must be performed. After the AUTO REFRESH cycles

are complete, the SDRAM is ready for mode register

programming. Because the mode register will power

up in an unknown state, it should be loaded prior to

applying any operational command.

Mode Register Definition

The mode register is used to define the specific

mode of operation of the SDRAM. This definition

includes the selection of a burst length, a burst type, a

CAS latency, an operating mode and a write burst

mode, as shown in Figure 5, Mode Register Definition

Diagram, on page 8. The mode register is programmed

via the LOAD MODE REGISTER command and will

retain the stored information until it is programmed

again or the device loses power.

Mode register bits M0–M2 specify the burst length,

M3 specifies the type of burst (sequential or inter-

leaved), M4–M6 specify the CAS latency, M7 and M8

specify the operating mode, M9 specifies the write

burst mode, and M10 and M11 are reserved for future

use.

The mode register must be loaded when all device

banks are idle, and the controller must wait the speci-

fied time before initiating the subsequent operation.

Violating either of these requirements will result in

unspecified operation.

Burst Length

Read and write accesses to the SDRAM are burst ori-

ented, with the burst length being programmable, as

shown in Figure 5, Mode Register Definition Diagram,

on page 8. The burst length determines the maximum

number of column locations that can be accessed for a

given READ or WRITE command. Burst lengths of 1, 2,

4, or 8 locations are available for both the sequential

and the interleaved burst types, and a full-page burst is

available for the sequential type. The full-page burst is

used in conjunction with the BURST TERMINATE

command to generate arbitrary burst lengths.

Reserved states should not be used, as unknown

operation or incompatibility with future versions may

result.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached, as shown in the Burst

Definition Table. The block is uniquely selected by A1–

A9 when the burst length is set to two; A2–A9 when the

burst length is set to four; and by A3–A9 when the burst

length is set to eight. The remaining (least significant)

address bit(s) is (are) used to select the starting loca-

tion within the block. Full-page bursts wrap within the

page if the boundary is reached, as shown in Table 7,

Burst Definitions, on page 9.

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved; this is referred to

as the burst type and is selected via bit M3.

The ordering of the accesses within a burst is deter-

mined by the burst length, the burst type, and the

starting column adress, as shown in Table 7, Burst Def-

initions, on page 9.

Figure 5: Mode Register Definition