512Mb: 32 Meg x 16, 16 Meg x 32 Mobile DDR SDRAM

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‡

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Micron Technology, Inc., reserves the right to change products or specifications without notice.

MT46H32M16.fm - Rev. A 03/05 EN

1

©2005 Micron Technology, Inc. All rights reserved.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron

to meet Micron’s production data sheet specifications.

Mobile Double Data Rate (DDR) SDRAM

MT46H32M16LF – 8 Meg x 16 x 4 Banks

MT46H16M32LF – 4 Meg x 32 x 4 Banks

For a complete data sheet, please refer to www.micron.com/mobileds.

Features

• Bidirectional data strobe per byte of data (DQS)

• Internal, pipelined double data rate (DDR)

architecture; two data accesses per clock cycle

• Differential clock inputs (CK and CK#)

• Commands entered on each positive CK edge

• DQS edge-aligned with data for READs; center-

aligned with data for WRITEs

• Four internal banks for concurrent operation

• Data masks (DM) for masking write data–one mask

per byte

• Programmable burst lengths: 2, 4, 8, 16 or full page

• Concurrent auto precharge option is supported

• Auto refresh and self refresh modes

• 1.8V LVCMOS compatible inputs

• On-chip temperature sensor to control refresh rate

• Partial array self refresh (PASR)

• Deep power-down (DPD)

• Selectable output drive (DS)

• Clock stop capability

Notes:1. Only available for x16 configuration.

2. Only available for x32 configuration.

Options

Marking

• 1.8V/1.8V

H

• Configuration

• 32 Meg x 16(8 Meg x 16 x 4 banks)

• 16 Meg x 32 (4 Meg x 32 x 4 banks)

32M16

16M32

•Plastic Package

TBD

• Timing – Cycle Time

•6ns @ CL = 3

• 7.5ns @ CL = 3

• 10ns @ CL = 3

-6

-75

-10

• Operating Temperature Range

• Commercial (0° to +70°C)

• Industrial (-40°C to +85°C)

None

IT

Figure 1: 60-Ball VFBGA Assignment

Table 1:

Configuration Addressing

Architecture

32 Meg x 16

16 Meg x 32

Configuration

8 Meg x 16 x 4

4 Meg x 32 x 4

Refresh Count

8K

8K

Row Addressing

8K (A0–A12)

8K (A0–A12)

Bank Addressing

4 (BA0, BA1)

4 (BA0, BA1)

Column Addressing

1K (A0–A9)

512 (A0–A8)

1234

6789

5

A

B

C

D

E

F

G

H

J

K

DQ14

DQ12

DQ10

DQ8

NC

CK#

A12

A8

A5

CKE

A9

A6

DQ15

DQ13

DQ11

DQ9

UDQS

UDM

CK

A11

A7

A4

DQ1

DQ3

DQ5

DQ7

WE#

CS#

A2

DQ0

DQ2

DQ4

DQ6

LDQS

LDM

CAS#

BA0

A0

A3

RAS#

BA1

A1