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MT32LD3264AG-6X Datasheet(PDF) 7 Page - Micron Technology |
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MT32LD3264AG-6X Datasheet(HTML) 7 Page - Micron Technology |
7 / 27 page 7 8, 16, 32 Meg x 64 Nonbuffered DRAM DIMMs Micron Technology, Inc., reserves the right to change products or specifications without notice. DM78.p65 – Rev. 2/99 ©1999, Micron Technology, Inc. 8, 16, 32 MEG x 64 NONBUFFERED DRAM DIMMs SPD ACKNOWLEDGE Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (Figure 3). The SPD device will always respond with an ac- knowledge after recognition of a start condition and its slave address. If both the device and a write opera- tion have been selected, the SPD device will respond with an acknowledge after the receipt of each subse- quent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowl- edge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will termi- nate further data transmissions and await the stop condition to return to standby power mode. SPD CLOCK AND DATA CONVENTIONS Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2). SPD START CONDITION All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD STOP CONDITION All communications are terminated by a stop con- dition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. SCL from Master Data Output from Transmitter Data Output from Receiver 9 8 Acknowledge Figure 3 Acknowledge Response From Receiver Figure 1 Data Validity Figure 2 Definition of Start and Stop SCL SDA DATA STABLE DATA STABLE DATA CHANGE SCL SDA START BIT STOP BIT |
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