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PDM41256SA7TSO Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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PDM41256SA7TSO Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
7 / 8 page PDM41256 Rev. 2.0 - 7/17/96 3-39 1 2 3 4 5 6 7 8 9 10 11 12 Low VCC Data Retention Waveform Data Retention Electrical Characteristics (LA Version Only) NOTES: (For three previous Electrical Characteristics tables) 1. The device is continuously selected. Chip Enable is held in its active state. 2. The address is valid prior to or coincident with the latest occuring Chip Enable. 3. At any given temperature and voltage condition, tHZCE is less than tLZCE. 4. This parameter is sampled. 5. The parameter is tested with CL = 5 pF as shown in Figure 2. Transition is measured ±200 mV from steady state voltage 6. Vcc = 5V ± 5%. Symbol Parameter Test Conditions Min. Typ. Max. Unit VDR VCC for Retention Data 2 — — V ICCDR Data Retention Current CE ≥ V CC – 0.2V VIN ≥ VCC – 0.2V or ≤ 0.2V VCC = 2V — 95 500 µA VCC = 3V — 350 750 µA tCDR Chip Deselect to Data Retention Time 0 — — ns tR (4) Operation Recovery Time tRC — — ns |
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