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PE12316 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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PE12316 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 29 page  PE12316 Triple Incremental Encoder February 6, 2003 Preliminary (Version 1.1) February 6, 2003 (Preliminary Version 1.1) Page 9/29 PE12316 MODE 6: Pulse Width Measurement Mode In this mode, Ua1n acts as a gate, and is the pulse width to be measured. Synchronised with the clock edge after a low to high transition in Ua1n, counting begins at the input clock frequency. Similarly, synchronised with the clock edge after a high to low transition of Ua1n, counting is disabled; the value in the counter is loaded in the output register; /KLI-KLOn is pulled low; and then the counter clears. See Figure 6. If Ua2n is held high, the counter will count up, and if Ua2n is held low, the counter will count down. Each counter can be preloaded in two or three bytes depending on 16 Bit or 24 Bit Mode by activating /CS, and /WE, and selecting the required byte with /A0 and /A3, and the required channel with /A1 and /A2. This must be done while Ua1n is low. The output register should be read by activating /CS, /RD, and selecting the individual bytes with /A0 after Ua1n has fallen and before the next preload takes place. The KLI-KLOn signal may be used as an interrupt to indicate to the processor when the output register has been loaded. In both the pulse width and frequency modes, the output register will not be loaded via /CS and /RD, but by the falling edge of Ua1n, or by pulling /KLI-KLOn low. Figure 6 Pulse Width Measurement |
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