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PZ3064 Datasheet(PDF) 9 Page - NXP Semiconductors |
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PZ3064 Datasheet(HTML) 9 Page - NXP Semiconductors |
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9 / 20 page  Philips Semiconductors Product specification PZ3064 64 macrocell CPLD 1997 Mar 05 89 DC ELECTRICAL CHARACTERISTICS FOR INDUSTRIAL GRADE DEVICES Industrial: –40 °C ≤ Tamb ≤ +85°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER TEST CONDITIONS MIN. MAX. UNIT VIL Input voltage low VDD = 3.0V 0.8 V VIH Input voltage high VDD = 3.6V 2.0 V VI Input clamp voltage VDD = 3.0V, IIN = –18mA –1.2 V VOL Output voltage low VDD = 3.0V, IOL = 8mA 0.5 V VOH Output voltage high VDD = 3.0V, IOH = –8mA 2.4 V II Input leakage current VIN = 0 to VDD –10 10 µA IOZ 3-Stated output leakage current VIN = 0 to VDD –10 10 µA IDDQ Standby current VDD = 3.6V, Tamb = –40°C 50 µA I 1 Dynamic current VDD = 3.6V, Tamb = –40°C @ 1MHz 1 mA IDDD1 Dynamic current VDD = 3.6V, Tamb = –40°C @ 50MHz 40 mA IOS Short circuit output current 1 pin at a time for no longer than 1 second –5 –130 mA CIN Input pin capacitance Tamb = 25°C, f = 1MHz 8 pF CCLK Clock input capacitance Tamb = 25°C, f = 1MHz 5 12 pF CI/O I/O pin capacitance Tamb = 25°C, f = 1MHz 10 pF NOTE: 1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded. Inputs are tied to VDD or ground. This parameter guaranteed by design and characterization, not testing. AC ELECTRICAL CHARACTERISTICS1 FOR INDUSTRIAL GRADE DEVICES Industrial: –40 °C ≤ Tamb ≤ +85°C; 3.0V ≤ VDD ≤ 3.6V SYMBOL PARAMETER I12 I15 UNIT SYMBOL PARAMETER MIN. MAX. MIN. MAX. UNIT tPD_PAL Propagation delay time, input (or feedback node) to output through PAL 2 12 2 15 ns tPD_PLA Propagation delay time, input (or feedback node) to output through PAL & PLA 3 14.5 3 17.5 ns tCO Clock to out delay time 2 8 2 9 ns tSU_PAL Setup time (from input or feedback node) through PAL 7 8 ns tSU_PLA Setup time (from input or feedback node) through PAL + PLA 9.5 10.5 ns tH Hold time 0 0 ns tCH Clock High time 5 5 ns tCL Clock Low time 5 5 ns tR Input Rise time 20 20 ns tF Input Fall time 20 20 ns fMAX1 Maximum FF toggle rate2 (1/tCH + tCL) 100 100 MHz fMAX2 Maximum internal frequency2 (1/tSUPAL + tCF) 74 65 MHz fMAX3 Maximum external frequency2 (1/tSUPAL + tCO) 67 58 MHz tBUF Output buffer delay time 1.5 1.5 ns tPDF_PAL Input (or feedback node) to internal feedback node delay time through PAL 10.5 13.5 ns tPDF_PLA Input (or feedback node) to internal feedback node delay time through PAL+PLA 13 16 ns tCF Clock to internal feedback node delay time 6.5 7.5 ns tINIT Delay from valid VDD to valid reset 50 50 µs tER Input to output disable3 14 15 ns tEA Input to output valid 14 15 ns tRP Input to register preset 16 17 ns tRR Input to register reset 16 17 ns NOTES: 1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating. 2. This parameter guaranteed by design and characterization, not by test. 3. Output CL = 5pF. |
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