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PZ3064I15BB1 Datasheet(PDF) 2 Page - NXP Semiconductors |
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2 / 20 page Philips Semiconductors Product specification PZ3064 64 macrocell CPLD 82 1997 Mar 05 853–1891 17824 FEATURES • Industry’s first TotalCMOS™ PLD – both CMOS design and process technologies • Fast Zero Power (FZP™) design technique provides ultra-low power and very high speed • High speed pin-to-pin delays of 10ns • Ultra-low static power of less than 50µA • Dynamic power that is 70% lower at 50MHz than competing devices • 100% routable with 100% utilization while all pins and all macrocells are fixed • Deterministic timing model that is extremely simple to use • 4 clocks with programmable polarity at every macrocell • Support for complex asynchronous clocking • Innovative XPLA™ architecture combines high speed with extreme flexibility • 1000 erase/program cycles guaranteed • 20 years data retention guaranteed • Logic expandable to 37 product terms • PCI compliant • Advanced 0.5µ E2CMOS process • Security bit prevents unauthorized access • Design entry and verification using industry standard and Philips CAE tools • Reprogrammable using industry standard device programmers • Innovative Control Term structure provides either sum terms or product terms in each logic block for: – Programmable 3-State buffer – Asynchronous macrocell register preset/reset • Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources • Available in PLCC, TQFP, and PQFP packages • Available in both Commercial and Industrial grades Table 1. PZ3064 Features PZ3064 Usable gates 2000 Maximum inputs 68 Maximum I/Os 64 Number of macrocells 64 Propagation delay (ns) 10 Packages 44-pin PLCC, 44-pin TQFP, 68-pin PLCC, 84-pin PLCC, 100-pin PQFP DESCRIPTION The PZ3064 CPLD (Complex Programmable Logic Device) is the second in a family of Fast Zero Power (FZP ™) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 64 macrocell CPLD. With the FZP ™ design technique, the PZ3064 offers true pin-to-pin speeds of 10ns, while simultaneously delivering power that is less than 50 µA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70% lower at 50MHz. These devices are the first TotalCMOS ™ PLDs, as they use both a CMOS process technology and the patented full CMOS FZP ™ design technique. For 5V applications, Philips also offers the high speed PZ5064 CPLD that offers these features in a full 5V implementation. The Philips FZP ™ CPLDs introduce the new patent-pending XPLA™ (eXtended Programmable Logic Array) architecture. The XPLA ™ architecture combines the best features of both PLA and PAL ™ type structures to deliver high speed and flexible logic allocation that results in superior ability to make design changes with fixed pinouts. The XPLA ™ structure in each logic block provides a fast 10ns PAL™ path with 5 dedicated product terms per output. This PAL ™ path is joined by an additional PLA structure that deploys a pool of 32 product terms to a fully programmable OR array that can allocate the PLA product terms to any output in the logic block. This combination allows logic to be allocated efficiently throughout the logic block and supports as many as 37 product terms on an output. The speed with which logic is allocated from the PLA array to an output is only 2.5ns, regardless of the number of PLA product terms used, which results in worst case tPD’s of only 12.5ns from any pin to any other pin. In addition, logic that is common to multiple outputs can be placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The PZ3064 CPLDs are supported by industry standard CAE tools (Cadence, Mentor, Synopsys, Synario, Viewlogic, MINC), using text (Abel, VHDL, Verilog) and/or schematic entry. Design verification uses industry standard simulators for functional and timing simulation. Development is supported on personal computer, Sparc, and HP platforms. Device fitting uses either Minc or Philips Semiconductors-developed tools. The PZ3064 CPLD is reprogrammable using industry standard device programmers from vendors such as Data I/O, BP Microsystems, SMS, and others. PAL is a registered trademark of Advanced Micro Devices, Inc. |
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