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SI5364 Datasheet(PDF) 1 Page - Silicon Laboratories |
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SI5364 Datasheet(HTML) 1 Page - Silicon Laboratories |
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1 / 40 page  Rev. 2.2 7/04 Copyright © 2004 by Silicon Laboratories Si5364 Si5364 SONET/SDH PRECISION PORT CARD CLOCK IC Features Applications Description The Si5364 is a complete solution for ultra-low jitter high-speed clock generation and distribution in precision clocking applications, such as OC-192/OC-48 SONET/SDH line/ port cards. This device phase locks to one of three reference inputs in the range of 19.44 MHz and generates four synchronous clock outputs that can be independently configured for operation in the 19, 155, or 622 MHz range (1, 8, and 32x input clock). Silicon Laboratories DSPLL™ technology delivers phase-locked loop (PLL) functionality with unparalleled performance while eliminating external loop filter components, providing programmable loop parameters, and simplifying design. The on-chip reference monitoring and clock switching functions support Stratum 3/3E and SMC compatible clock switching with excellent output phase transient characteristics. FEC rates are supported with selectable 255/238 or 238/255 scaling of the clock multiplication ratios. The Si5364 establishes a new standard in performance and integration for ultra-low jitter clock generation. It operates from a single 3.3 V supply. Functional Block Diagram Ultra-low jitter clock outputs with jitter generation as low as 0.3 psRMS No external components (other than a resistor and standard bypassing) Up to three clock inputs Four independent clock outputs at 19, 155, or 622 MHz Stratum 3, 3E, and SMC compatible Digital hold for loss-of-input clock Automatic or manually-controlled hitless switching between clock inputs Revertive/non-revertive switching Loss-of-signal and frequency offset alarms for each clock input Support for forward and reverse FEC clock scaling 8 kHz frame sync output Low power Small size (11x11 mm) SONET/SDH line/port cards Terabit routers Core switches Digital cross connects FRQSEL_1[1:0] CLKOUT_1+ CLKOUT_1– 2 2 2 2 DSBLFSYNC FSYNC MANCNTRL[1:0] VALTIME A_ACTV LOS_A FOS_A LOS_B FOS_B LOS_F REF/CLKIN_F+ REF/CLKIN_F– CLKIN_B+ CLKIN_B– CLKIN_A+ CLKIN_A– AUTOSEL CAL_ACTV Signal Detection, Selection, & Control 2 2 2 SMC/S3N DSBLFOS RVRT B_ACTV F_ACTV DH_ACTV RSTN/CAL FEC[1:0] BWSEL[1:0] 2 CLKOUT_2+ CLKOUT_2– CLKOUT_3+ CLKOUT_3– CLKOUT_4+ CLKOUT_4– FRQSEL_2[1:0] FRQSEL_3[1:0] FRQSEL_4[1:0] SYNCIN Biasing & Supply REXT VSEL33 VDD GND ÷ ÷ ÷ ÷ ÷ 2 SiLECTTM Switching DSPLLTM FXDDELAY INCDELAY DECDELAY Ordering Information: See page 36. Si5364 Bottom View |
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