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SMJ44C251 Datasheet(PDF) 6 Page - Texas Instruments |
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SMJ44C251 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 53 page  SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM SGMS058A – MARCH 1995 – REVISED JUNE 1995 6 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 output enable / transfer select ( TRG) TRG selects either DRAM or transfer operation as RAS falls. For DRAM operation, TRG must be held high as RAS falls. During DRAM operation, TRG functions as an output enable for the DRAM outputs DQ0 – DQ3. For transfer operation, TRG must be brought low before RAS falls. write-mask select, write enable ( W ) In DRAM operation, W enables data to be written to the DRAM. W is also used to select the DRAM write-per-bit mode. Holding W low on the falling edge of RAS invokes the write-per-bit operation. The SMJ44C251B supports both the normal write-per-bit mode and the persistent write-per-bit mode. For transfer operation, W selects either a read-transfer operation (DRAM to SAM) or a write-transfer operation (SAM to DRAM). During a transfer cycle, if W is high when RAS falls, a read transfer occurs; if W is low, a write transfer occurs. special function select (DSF) DSF is latched on the falling edge of RAS or CAS, similar to an address. DSF determines which of the following functions are invoked on a particular cycle: D Persistent write-per-bit D Block write D Split-register transfer read D Mask-register load for the persistent write-per-bit mode D Color-register load for the block-write mode DRAM data I/O, write-mask data (DQ0 – DQ3) DRAM data is written via DQ terminals during a write or read-modify-write cycle. In an early-write cycle, W is brought low prior to CAS and the data is strobed in by CAS with data setup and hold times referenced to this signal. In a delayed-write or read-modify-write cycle, W is brought low after CAS and the data is strobed in by W with data setup and hold times referenced to this signal. The 3-state DQ output buffers provide direct TTL compatibility (no pullup resistors) with a fanout of two Series 54 TTL loads. Data out is the same polarity as data in. The outputs are in the high-impedance (floating) state as long as CAS and TRG are held high. Data does not appear at the outputs until both CAS and TRG are brought low. Once the outputs are valid, they remain valid while CAS and TRG are low. CAS or TRG going high returns the outputs to the high-impedance state. In a register-transfer operation, the DQ outputs remain in the high-impedance state for the entire cycle. The write-per-bit mask is latched into the device via the random DQ terminals by the falling edge of RAS. This mask selects which of the four random I/Os are written. serial data I/O (SDQ0 – SDQ3) Serial inputs and serial outputs share common I/O terminals. Serial-input or serial-output mode is determined by the previous transfer cycle. If the previous transfer cycle was a read transfer, the data register is in serial-output mode. While in serial-output mode, data in SAM is accessed from the least significant bit to the most significant bit. The data registers operate modulo 512; so after bit 511 is accessed, the next bits to be accessed are 00, 01, 02, etc. If the previous transfer cycle was either a write transfer or a pseudo transfer, the data register is in serial-input mode and signal data can be input to the register. serial clock (SC) Serial data is accessed in or out of the data register on the rising edge of SC. The SMJ44C251B is designed to work with a wide range of clock-duty cycles to simplify system design. There is no refresh requirement because the data registers that comprise the SAM are static. There is also no minimum SC clock operating frequency. |
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