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SST25VF512 Datasheet(PDF) 3 Page - Silicon Storage Technology, Inc |
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SST25VF512 Datasheet(HTML) 3 Page - Silicon Storage Technology, Inc |
3 / 23 page Data Sheet 512 Kbit SPI Serial Flash SST25VF512 3 ©2005 Silicon Storage Technology, Inc. S71192-08-000 11/05 PIN DESCRIPTION FIGURE 1: PIN ASSIGNMENTS FIGURE 2: SPI PROTOCOL TABLE 1: PIN DESCRIPTION Symbol Pin Name Functions SCK Serial Clock To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. SI Serial Data Input To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. SO Serial Data Output To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of any command sequence. WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register. HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device. VDD Power Supply To provide power supply (2.7-3.6V). VSS Ground T1.7 1192 1 2 3 4 8 7 6 5 CE# SO WP# VSS VDD HOLD# SCK SI Top View 1192 08-soic P1.4 8-LEAD SOIC 8-CONTACT WSON 1 2 3 4 8 7 6 5 CE# SO WP# VSS Top View VDD HOLD# SCK SI 1192 08-wson P1a.6 1192 F34.6 MODE 3 SCK SI SO CE# MODE 3 DON'T CARE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MODE 0 MODE 0 HIGH IMPEDANCE MSB MSB |
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