TE

CH

tm

T436416A

TM Technology Inc. reserves the right

P. 7

Publication Date: MAY. 2003

to change products or specifications without notice.

Revision: B

OPERATING AC PARAMETER

(AC opterating conditions unless otherwise noted)

Speed Version

Parameter

Symbol

-6

-7

-7.5

-8

-10

Unit

Note

Row active to row active delay

12

14

15

16

20

ns

1

RAS to CAS delay

16

18

18

20

20

ns

1

Row precharge time

18

20

20

20

20

ns

1

42

42

45

48

50

ns

1

Row active time

100K

ns

Row cycle time

60

63

65

68

70

ns

1

Last data in to new col. Address delay

1

CLK

2

Last data in to row precharge

2

CLK

2

Last data in to burst stop

1

CLK

2

Col. Address to col. Address delay

1

CLK

3

CAS latency=3

1

Number of valid output data

CAS latency=2

1

ea

4

with clock cycle time and then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

The earliest a precharge command can be issued after a Read command without the loss of data is

CL + BL-2 clocks.