T436416A-10SG datasheet(3/29 Pages) TMT

Part #	T436416A-10SG

Description	4M X 16 SDRAM

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Manufacturer	TMT [Taiwan Memory Technology]

Direct Link	http://www.tmtech.com.tw

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TE

CH

tm

T436416A

TM Technology Inc. reserves the right

P. 3

Publication Date: MAY. 2003

to change products or specifications without notice.

Revision: B

PIN DESCRIPTION

NAME

INPUT FUNCTION

CLK

System Clock

Active on the positive going edge to sample all input.

CS

Chip Select

Disables or enables device operation by masking or enabling all input

except CLK,CKE and L(U)DQM

CKE

Clock Enable

Masks system clock to freeze operation from the next clock cycle.

CKE should be enabled at least one cycle prior to new command.

Disable input buffers for power down in standby.

A0 ~ A11

Address

Row/column addresses are multiplexed on the same pins.

Row address : RA0 ~ RA11,column address : CA0 ~ CA7

BA0 ~ BA1

Bank Select Address

Selects bank to be activated during row address latch time.

Select bank for read/write during column address latch time.

RAS

Row Address Strobe

Latches row addresses on the positive going edge of the CLK

with

RAS low.

Enables row access & precharge.

CAS

Column Address Strobe

Latches column addresses on the positive going edge of the CLK

with

CAS low.

Enables column access .

WE

Write Enable

Enables write operation and row precharge.

Latches data in starting from

CAS , WE active.

L(U)DQM

Data Input/Output

Mask

Makes data output Hi-Z,

tSHZ after the clock and masks the output.

Blocks data input when L(U)DQM active.

DQ0 ~ DQ15

Data Input/Output

Data inputs/outputs are multiplexed on the same pins.

VDD/VSS

Power Supply/Ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ

Data Output

Power/Ground

Isolated power supply and ground for the output buffers to provide

improved noise immunity.

N.C/RFU

No

Connection/Reserved

for Future Use

This pin is recommended to be left No Connection on the device.

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