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TMC93LC46 Datasheet(PDF) 7 Page - List of Unclassifed Manufacturers |
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TMC93LC46 Datasheet(HTML) 7 Page - List of Unclassifed Manufacturers |
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7 / 15 page  7 93LC46/56/57/66/86 Doc. No. 1023, Rev. G The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93LC46)/ /7-bit (93LC57)/ 8-bit (93LC56 or 93LC66)/10-bit (93LC86) (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations). Note: This note is applicable only to 93LC86. The Write, Erase, Write all and Erase all instructions require PE=1. If PE is left floating, 93C86 is in Program Enabled mode. For Write Enable and Write Disable instruction PE=don’t care. Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the 93LC46/ 56/57/66/86 will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1). For the 93LC56/57/66/86, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the 93LC46/56/57/66/86 can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Figure 3. Write Instruction Timing 93LC46/56/57/66/86 F05 Figure 2b. Read Instruction Timing (93LC56/57/66/86) SK CS DI DO HIGH-Z 11 0 AN AN–1 A0 Dummy 0 D15 . . . D0 or D7 . . . D0 1 1 1 1 1 1 1 1 1111111 Address + 1 D15 . . . D0 or D7 . . . D0 Address + 2 D15 . . . D0 or D7 . . . D0 Address + n D15 . . . or D7 . . . Don't Care SK CS DI DO tCSMIN STANDBY HIGH-Z HIGH-Z 101 AN AN-1 A0 DN D0 BUSY READY STATUS VERIFY tSV tHZ tEW |
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