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AS7C3364PFS36A-166TQI Datasheet(PDF) 10 Page - Alliance Semiconductor Corporation |
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AS7C3364PFS36A-166TQI Datasheet(HTML) 10 Page - Alliance Semiconductor Corporation |
10 / 11 page AS7C3364PFS32A AS7C3364PFS36A ® 2/1/01 Alliance Semiconductor P. 10 of 11 AC test conditions Notes 1 For test conditions, see AC Test Conditions, Figures A, B, C. 2 This parameter measured with output load condition in Figure C. 3 This parameter is sampled, but not 100% tested. 4tHZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage. 5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL. 6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs must meet the setup and hold times for all rising edges of CLK when chip is enabled. 7 Write refers to GWE, BWE, BW[a:d]. 8 Chip select refers to CE0, CE1, CE2. 351 Ω 5 pF* 317 Ω DOUT GND Figure C: Output load(B) *including scope and jig capacitance Z0 = 50Ω DOUT 50 Ω Figure B: Output load (A) 30 pF* Figure A: Input waveform 10% 90% GND 90% 10% +3.0V • Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure C. • Input pulse level: GND to 3V. See Figure A. • Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A. • Input and output timing reference levels: 1.5V. VL = 1.5V for 3.3V I/O; = VDDQ/2 for 2.5V I/O Thevenin equivalent: +3.3V for 3.3V I/O; +2.5V for 2.5V I/O Package Dimensions 100-pin quad flat pack (TQFP) Dimensions in millimeters TQFP Min Max A1 0.05 0.15 A2 1.35 1.45 b 0.22 0.38 c 0.09 0.20 D 13.90 14.10 E 19.90 20.10 e 0.65 nominal Hd 15.90 16.10 He 21.90 22.10 L 0.45 0.75 L1 1.00 nominal α 0° 7° He E Hd D b e A1 A2 L1 L c α |
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