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CY7C182
3
Switching Characteristics Over the Operating Range
Parameter
Description
7C182-25
7C182-35
7C182-45
Unit
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE[4]
tRC
Read Cycle Time
25
35
45
ns
tAA
Address to Data Valid
25
35
45
ns
tOHA
Data Hold from Address Change
3
3
3
ns
tACE1
CE1 Access Time
25
35
45
ns
tACE2
CE2 Access Time
25
35
45
ns
tLZCE1
CE1 LOW to Low Z
5
5
5
ns
tLZCE2
CE2 HIGH to Low Z
5
5
5
ns
tHZCE1
CE1 HIGH to High Z
[5]
18
20
25
ns
tHZCE2
CE2 LOW to High Z
[5]
18
20
25
tPU
CE1 LOW to Power-Up
0
0
0
ns
tPD
CE1 HIGH to Power-Down
20
20
25
ns
tDOE
OE Access Time
18
20
20
ns
tLZOE
OE LOW to Low Z
3
3
3
ns
tHZOE
OE HIGH to High Z[5]
18
20
25
ns
WRITE CYCLE[6]
tWC
Write Cycle Time
25
35
45
ns
tSA
Address Set-Up Time
0
0
0
ns
tAW
Address Valid to End of Write
20
30
40
ns
tSD
Data Set-Up Time
15
20
25
ns
tSCE1
CE1 LOW to Write End
20
30
40
ns
tSCE2
CE2 HIGH to Write End
20
30
40
ns
tPWE
WE Pulse Width
20
25
30
ns
tHA
Address Hold from End of Write
0
0
0
ns
tHD
Data Hold Time
0
0
0
ns
tLZWE
Write HIGH to Low Z[7]
3
3
3
ns
tHZWE
Write LOW to High Z[5, 7, 8]
13
15
20
ns
Notes:
4.
WE is HIGH for read cycle.
5.
tHZCE and tHZWE are specified with CL = 5 pF. Transition is measured ± 500 mV from steady-state voltage.
6.
The internal write time of the memory is defined by the overlap of CE1 LOW, CE2 HIGH, and WE LOW. All three signals must be asserted to initiate a write
and any signal can terminate a write by being deasserted. The data input set-up and hold timing should be referenced to the rising edge of the signal that
terminates the write.
7.
At any given temperature and voltage condition, tLZWE is less than tHZWE for any given device. These parameters are sampled and not 100% tested.
8.
Address valid prior to or coincident with CE transition LOW and CE2 transition HIGH.
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