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HOTLink II™ SMPTE Receiver Training Clock
CY24130
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07711 Rev. **
Revised February 04, 2005
Features
• Integrated phase-locked loop
• Low-jitter, high-accuracy outputs
• 3.3V operation
Benefits
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system
designs
• Enables application compatibility
Part Number
Outputs
Input Frequency
Output Frequency Range
CY24130-1
2
27 MHz (Driven Reference)
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
CY24130-2
2
27 MHz (Crystal Reference)
1 copy 27-MHz reference clock output
1 copy of 27-/36-/54-/148.5-/74.25-MHz (frequency selectable)
XIN
XOUT
OUTPUT
MULTIPLEXER
AND
DIVIDERS
PLL
OSC.
CLKA
Q
P
VCO
VDDL
AVSS
Φ
AVDD
VSS
S0
S1
REFCLK
16-pin TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VSS
VSSL
S1
XIN
XOUT
VDD
S0
AVSS
N/C
S2
REFCLK
AVDD
VDDL
N/C
N/C
CLKA
S2
CY24130-1, -2
Pin Configuration
VDD
VSSL
Logic Block Diagram
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