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IDT71V2556S Datasheet(PDF) 1 Page - Integrated Device Technology

Part # IDT71V2556S
Description  128K x 36, 256K x 18 3.3V Synchronous ZBT SRAMs 2.5V I/O, Burst Counter Pipelined Outputs
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT71V2556S Datasheet(HTML) 1 Page - Integrated Device Technology

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OCTOBER 2004
DSC-4875/08
1
©2004 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbuscycles
when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBTTM, or Zero Bus
Turnaround.
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
Features
x
x
x
x
x
128K x 36, 256K x 18 memory configurations
x
x
x
x
x
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
x
x
x
x
x
ZBTTM Feature - No dead cycles between write and read
cycles
x
x
x
x
x
Internally synchronized output buffer enable eliminates the
need to control
OE
OE
OE
OE
OE
x
x
x
x
x
Single R/
W
W
W
W
W (READ/WRITE) control pin
x
x
x
x
x
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x
x
x
x
x
4-word burst capability (interleaved or linear)
x
x
x
x
x
Individual byte write (
BW
BW
BW
BW
BW1 - BW
BW
BW
BW
BW4) control (May tie active)
x
x
x
x
x
Three chip enables for simple depth expansion
x
x
x
x
x
3.3V power supply (±5%), 2.5V I/O Supply (VDDQ)
x
x
x
x
x
Optional - Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
x
x
x
x
x
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
A0-A17
Address Inputs
Input
Synchronous
CE1, CE2, CE2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW1, BW2, BW3, BW4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O0-I/O31, I/OP1-I/OP4
Data Input / Output
I/O
Synchronous
VDD, VDDQ
Core Power, I/O Power
Supply
Static
VSS
Ground
Supply
Static
4875 tbl 01
IDT71V2556S
IDT71V2558S
IDT71V2556SA
IDT71V2558SA
128K x 36, 256K x 18
3.3V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
cycle, and two cycles later the associated data cycle occurs, be it read
or write.
The IDT71V2556/58 contain data I/O, address and control signal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
to disable the outputs at any given time.
A Clock Enable (
CEN)pinallowsoperationoftheIDT71V2556/58to
be suspended as long as necessary. All synchronous inputs are ignored
when(
CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
There are three chip enable pins (
CE1,CE2,CE2) that allow the user
to deselect the device when desired. If any one of these three are not
assertedwhenADV/
LDislow,nonewmemoryoperationcanbeinitiated.
However, any pending data transfers (reads or writes) will be completed.
The data bus will tri-state two cycles after chip is deselected or a write is
initiated.
The IDT71V2556/58 has an on-chip burst counter. In the burst mode,
the IDT71V2556/58 can provide four cycles of data for a single address
presentedtotheSRAM.Theorderoftheburstsequenceisdefinedbythe
LBOinputpin.TheLBOpinselectsbetweenlinearandinterleavedburst
sequence. The ADV/
LD signal is used to load a new external address
(ADV/
LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V2556/58 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).


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