IC41C4405x and IC41LV4405x Series

2

Integrated Circuit Solution Inc.

DR013-0B 10/17/2002

FEATURES

• Fast Page Mode Access Cycle

• TTL compatible inputs and outputs

• Refresh Interval:

-- 2,048 cycles/32 ms

-- 4,096 cycles/64 ms

• Refresh Mode:

RAS-Only,

CAS-before-RAS (CBR), and Hidden

• JEDEC standard pinout

• Single power supply:

5V ± 10% or 3.3V ± 10%

• Byte Write and Byte Read operation via

two

CAS

DESCRIPTION

The

CMOS Dynamic Random Access Memory. The Fast Page

Mode allows 2,048 or 4096 random accesses within a single

row with access cycle time as short as 20 ns per 4-bit word.

These features make the 4405x Series ideally suited for high-

bandwidth graphics, digital signal processing, high-performance

computing systems, and peripheral applications.

The 4405x Series is packaged in a 24-pin 300mil SOJ and a 24

pin TSOP-2

4M x 4 (16-MBIT) DYNAMIC RAM

WITH FAST PAGE MODE

KEY TIMING PARAMETERS

Parameter

-

50

-

60

Unit

0

6

0

ns

15

ns

30

ns

25

ns

8

4

104

ns

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.

PRODUCT SERIES OVERVIEW

Part No.

Refresh

Voltage

IS41C44052

2K

5

V±10%

IS41C44054

4K

5

V±10%

IS41LV44052

2K

3.3V ± 10%

IS41LV44054

4K

3.3V ± 10%

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13

VCC

I/O0

I/O1

WE

RAS

*A11(NC)

A10

A0

A1

A2

A3

VCC

GND

I/O3

I/O2

CAS

OE

A9

A8

A7

A6

A5

A4

GND

* A11 is NC for 2K Refresh devices.

PIN DESCRIPTIONS

A0-A11

Address Inputs (4K Refresh)

A0-A10

Address Inputs (2K Refresh)

I/O0-3

Data Inputs/Outputs

WE

Write Enable

OE

Output Enable

RAS

Row Address Strobe

CAS

Column Address Strobe

V

cc

Power

GND

Ground

NC

No Connection

PIN CONFIGURATION

24 (26) Pin SOJ, TSOP-2