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IDT70T3319S200DD Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT70T3319S200DD Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 28 page  6.42 IDT70T3339/19/99S PRELIMINARY High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges 6 Pin Names NOTES: 1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2. OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another—both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3. When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/ FTx and OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode. 5. Due to limited pin count, JTAG, Collision Detection and Interrupt are not supported in the DD-144 package. 6. Address A18x is a NC for the IDT70T3319. Also, Addresses A18x and A17x are NC's for the IDT70T3399. 7. Chip Enables and Byte Enables are double buffered when PL/ FT = VIH, i.e., the signals take two cycles to deselect. Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables (Input)(7) R/ WL R/ WR Read/Write Enable (Input) OEL OER Output Enable (Input) A0L - A18L (6) A0R - A18R (6) Address (Input) I/O0L - I/O17L I/O0R - I/O17R Data Input/Output CLKL CLKR Clock (Input) PL/ FTL PL/ FTR Pipeline/Flow-Through (Input) ADSL ADSR Address Strobe Enable (Input) CNTENL CNTENR Counter Enable (Input) REPEATL REPEATR Counter Repeat(3) UBL UBR Upper Byte Enable (I/O9 - I/O17) (7) LBL LBR Lower Byte Enable (I/O0 - I/O8)(7) VDDQL VDDQR Power (I/O Bus) (3.3V or 2.5V)(1) (Input) OPTL OPTR Option for selecting VDDQX(1,2) (Input) ZZL ZZR Sleep Mode pin(4) (Input) VDD Power (2.5V) (1) (Input) VSS Ground (0V) (Input) TDI(5) Test Data Input TDO(5) Test Data Output TCK(5) Test Logic Clock (10MHz) (Input) TMS(5) Test Mode Select (Input) TRST(5) Reset (Initialize TAP Controller) (Input) INTL(5) INTR(5) Interrupt Flag (Output) COLL(5) COLR(5) Collision Alert (Output) 5652 tbl 01 |
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