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IDT71V2556S133PF Datasheet(PDF) 11 Page - Integrated Device Technology |
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IDT71V2556S133PF Datasheet(HTML) 11 Page - Integrated Device Technology |
11 / 28 page 6.42 IDT71V2556, IDT71V2558, 128K x 36, 256K x 18, 3.3V Synchronous ZBT™ SRAMs with 2.5V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges 11 NOTES: 1. H = High; L = Low; X = Don’t Care; Z = High Impedance. 2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. Read Operation(1) Device Operation - Showint Mixed Load, Burst, Deselect and NOOP Cycles(2) NOTES: 1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L. 2. H = High; L = Low; X = Don’t Care; Z = High Impedance. Cycle Address R/ W ADV/ LD CE(1) CEN BWx OE I/O Comments nA0 H L L L X X X Load read n+1 X X H X L X X X Burst read n+2 A1 HL L L X L Q0 Load read n+3 X X L H L X L Q0+1 Deselect or STOP n+4 X X H XL XL Q1 NOOP n+5 A2 H L L L X X Z Load read n+6 X X H X L X X Z Burst read n+7 X X L H L X L Q2 Deselect or STOP n+8 A3 L L LLLL Q2+1 Load write n+9 X X H X L L X Z Burst write n+10 A4 L L LLL X D3 Load write n+11 X X L H L X X D3+1 Deselect or STOP n+12 X X H X L X X D4 NOOP n+13 A5 L L LLL X Z Load write n+14 A6 H L L L X X Z Load read n+15 A7 L L LLL X D5 Load write n+16 X X H X LLL Q6 Burst write n+17 A8 HL L L X X D7 Load read n+18 X X H X L X X D7+1 Burst read n+19 A9 L L LLLL Q8 Load write 4875 tbl 12 Cycle Address R/ W ADV/ LD CE(2) CEN BWx OE I/O Comments nA0 H L L L X X X Address and Control meet setup n+1 X X X X L X X X Clock Setup Valid n+2 X X X XXX L Q0 Contents of Address A0 Read Out 4875 tbl 13 |
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