M48T58-70PC1 datasheet(10/27 Pages) STMICROELECTRONICS

Part #	M48T58-70PC1

Description	5.0V, 64 Kbit (8 Kb x 8) TIMEKEEPER SRAM

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Manufacturer	STMICROELECTRONICS [STMicroelectronics]

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10 / 27 page

M48T58, M48T58Y

10/27

READ Mode

The M48T58/Y is in the READ Mode whenever W

(WRITE Enable) is high, E1 (Chip Enable 1) is low,

and E2 (Chip Enable 2) is high. The unique ad-

dress specified by the 13 Address Inputs defines

which one of the 8,192 bytes of data is to be ac-

cessed. Valid data will be available at the Data I/O

pins within Address Access time (tAVQV)after the

last address input signal is stable, providing that

the E1, E2, and G access times are also satisfied.

If the E1,E2 and G access times are not met, valid

data will be available after the latter of the Chip En-

able Access times (tE1LQV or tE2HQV)orOutput

Enable Access time (tGLQV).

The state of the eight three-state Data I/O signals

is controlled by E1,E2 and G. If the outputs are ac-

tivated before tAVQV, the data lines will be driven to

an indeterminate state until tAVQV. If the Address

Inputs are changed while E1, E2 and G remain ac-

tive, output data will remain valid for Output Data

Hold time (tAXQX) but will go indeterminate until the

next Address Access.

Figure 8. READ Mode AC Waveforms

Note: WRITE Enable (W)= High.

AI00962

tAVAV

tAVQV

tAXQX

tE1LQV

tE1LQX

tE1HQZ

tGLQV

tGLQX

tGHQZ

VALID

A0-A12

E1

G

DQ0-DQ7

tE2HQV

tE2HQX

VALID

tE2LQZ

E2

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