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M381L5623MTN Datasheet(PDF) 3 Page - Samsung semiconductor |
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M381L5623MTN Datasheet(HTML) 3 Page - Samsung semiconductor |
3 / 17 page Preliminary 2GB Unbuffered DIMM Rev. 0.0 April 2004 DDR SDRAM SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice. Ordering Information Operating Frequencies Part Number Density Organization Component Composition Height M368L5623MTN-C(L)B3/A2/B0 2GB 128M x 64 128Mx8 (K4H1G0838M) * 16EA 1,250mil M381L5623MTM-C(L)B3/A2/B0 2GB 128M x 72 128Mx8 (K4H1G0838M) * 18EA 1,250mil B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) Speed @CL2 133MHz 133MHz 100MHz Speed @CL2.5 166MHz 133MHz 133MHz CL-tRCD-tRP 2.5-3-3 2-3-3 2.5-3-3 Feature • Power supply : Vdd: 2.5V ± 0.2V, Vddq: 2.5V ± 0.2V • Double-data-rate architecture; two data transfers per clock cycle • Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) • Differential clock inputs(CK and CK) • DLL aligns DQ and DQS transition with CK transition • Programmable Read latency 2, 2.5 (clock) • Programmable Burst length (2, 4, 8) • Programmable Burst type (sequential & interleave) • Edge aligned data output, center aligned data input • Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) • Serial presence detect with EEPROM • PCB : Height 1,250 (mil) & double sided • SSTL_2 Interface 184Pin Unbuffered DIMM based on 1Gb M-die (x8) |
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