Electronic Components Datasheet Search |
|
MAX1070 Datasheet(PDF) 11 Page - Maxim Integrated Products |
|
MAX1070 Datasheet(HTML) 11 Page - Maxim Integrated Products |
11 / 18 page Applications Information External Reference An external reference is required for the MAX1070/ MAX1071. Use a 4.7µF and 0.01µF bypass capacitor on the REF pin for best performance. The reference input structure allows a voltage range of +1V to VDD. How to Start a Conversion An analog-to-digital conversion is initiated by CNVST and clocked by SCLK, and the resulting data is clocked out on DOUT by SCLK. With SCLK idling high or low, a falling edge on CNVST begins a conversion. This causes the analog input stage to transition from track to hold mode, and DOUT to transition from high impedance to being actively driven low. A total of 16 SCLK cycles are required to complete a normal conversion. If CNVST is low during the 16th falling SCLK edge, DOUT returns to high impedance on the next rising edge of CNVST or SCLK, enabling the serial interface to be shared by multi- ple devices. If CNVST returns high after the 14th, but before the 16th SCLK rising edge, DOUT remains active so continuous conversions can be sustained. The high- est throughput is achieved when performing continuous conversions. Figure 10 illustrates a conversion using a typical serial interface. Connection to Standard Interfaces The MAX1070/MAX1071 serial interface is fully compati- ble with SPI/QSPI and MICROWIRE (see Figure 11). If a serial interface is available, set the CPU’s serial interface in master mode so the CPU generates the serial clock. Choose a clock frequency up to 28.8MHz. SPI and MICROWIRE When using SPI or MICROWIRE, the MAX1070/MAX1071 are compatible with all four modes programmed with the CPHA and CPOL bits in the SPI or MICROWIRE control register. Conversion begins with a CNVST falling edge. DOUT goes low, indicating a conversion is in progress. Two consecutive 1-byte reads are required to get the full 10 bits from the ADC. DOUT transitions on SCLK rising edges. DOUT is guaranteed to be valid tDOUT later and remains valid until tDHOLD after the following SCLK rising edge. When using CPOL = 0 and CPHA = 0 or CPOL = 1 and CPHA = 1, the data is clocked into the µP on the following rising edge. When using CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA = 0, the data is clocked into the µP on the next falling edge. See Figure 11 for connections and Figures 12 and 13 for timing. See the Timing Characteristics section to determine the best mode to use. 1.5Msps, Single-Supply, Low-Power, True-Differential, 10-Bit ADCs ______________________________________________________________________________________ 11 OUTPUT CODE FULL-SCALE TRANSITION 111...111 12 3 0 FS FS - 3/2 LSB FS = VREF DIFFERENTIAL INPUT VOLTAGE (LSB) 1 LSB = VREF 1024 111...110 111...101 000...011 000...010 000...001 000...000 ZS = 0 Figure 8. Unipolar Transfer Function (MAX1070 Only) OUTPUT CODE FULL-SCALE TRANSITION FS 0 -FS FS - 3/2 LSB DIFFERENTIAL INPUT VOLTAGE (LSB) 011...111 011...110 000...010 000...001 000...000 111...111 111...110 111...101 100...001 100...000 1 LSB = VREF 1024 FS = VREF 2 - FS = -VREF 2 ZS = 0 Figure 9. Bipolar Transfer Function (MAX1071 Only) |
Similar Part No. - MAX1070 |
|
Similar Description - MAX1070 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |