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PC7410 Datasheet(PDF) 6 Page - ATMEL Corporation

Part # PC7410
Description  PowerPC 7410 RISC Microprocessor Product Specification
Download  54 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

PC7410 Datasheet(HTML) 6 Page - ATMEL Corporation

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PC7410
2141D–HIREL–02/04
32K 32-byte line, 8-way set associative data cache (dL1)
Single-cycle cache access
Pseudo least-recently-used (LRU) replacement
Data cache supports AltiVec LRU and transient instructions algorithm
Copy-back or write-through data cache (on a page-per-page basis)
Supports all PowerPC memory coherency modes
Non-blocking instruction and data cache
Separate copy of data cache tags for efficient snooping
No snooping of instruction cache except for ICBI instruction
Level 2 (L2) Cache Interface
Internal L2 cache controller and tags; external data SRAMs
512K, 1M and 2-Mbyte 2-way set associative L2 cache support
Copyback or write-through data cache (on a page basis or for all L2)
32-byte (512K), 64-byte (1M), or 128-byte (2M) sectored line size
Supports pipelined (register-register) synchronous burst SRAMs and
pipelined (register-register) late-write synchronous burst SRAMs
Supports direct mapped mode for 256K, 512K, 1M or 2 Mbytes of SRAM
(either all, half or none of L2 SRAM must be configured as direct mapped.
Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4
supported
64-bit data bus which also support 32-bits bus mode
Selectable interface voltages of 1.8V and 2.5V
Memory Management Unit
128 entry, 2-way set associative instruction TLB
128 entry, 2-way set associative data TLB
Hardware reload for TLBs
Four instruction BATs and four data BATs
Virtual memory support for up to four petabytes (2
52) of virtual memory
Real memory support for up to four gigabytes (2
32) of physical memory
Snooped and invalidated for TLBI instructions
Efficient Data Flow
All data buses between VRF, load/store unit, dL1, iL1, L2 and the bus are
128 bits wide
dL1 is fully pipelined to provide 128 bits per cycle to/from the VRF
L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s
Up to eight outstanding out-of-order cache misses between dL1 and L2/bus
Up to seven outstanding out-of-order transactions on the bus
Load folding to fold new dL1 misses into older outstanding load and store
misses to the same line
Store miss merging for multiple store misses to the same line. Only
coherency action taken (i.e., address only) for store misses merged to all 32
bytes of a cache line (no data tenure needed).
Two-entry finished store queue and four-entry completed store queue
between load/store unit and dL1


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