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PC87322VF Datasheet(PDF) 7 Page - National Semiconductor (TI) |
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PC87322VF Datasheet(HTML) 7 Page - National Semiconductor (TI) |
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7 / 84 page  10 Pin Description (Continued) Symbol Pin IO Function A9–A0 21–30 I Address These address lines from the microprocessor determine which internal register is accessed A0 – A9 are don’t cares during an FDC DMA transfer ACK 85 I Acknowledge This input is pulsed low by the printer to indicate that it has received data from the parallel port This pin has a nominal 25 kX pull-up resistor attached to it (See DR1 and Table 7-5 for further information AFD 78 IO Automatic Feed XT When this signal is low the printer should automatically line feed after each line is printed This pin is in a TRI-STATE condition 10 ns after a zero is loaded into the corresponding Control Register bit The system should pull this pin high using a 47 kX resistor (See DSTRB and Table 7-5 for further information) AEN 20 I Address Enable This input disables function selection via A9 – A0 when it is high Access to the FDC Data Register during DMA transfer is NOT affected by this pin ASTRB 81 O Address Strobe This signal is used in EPP mode as address strobe It is active low (See SLIN and Table 7-5 for further information) BADDR0 55 I Base Address This bit determines one of two base addresses from which the Index and Data Registers are offset (see Table 2-2) An internal pull-down resistor of 30 kX is on this pin Use a 10 kX resistor to pull this pin to VCC BOUT12 73 65 O BAUD Output This multi-function pin provides the associated serial channel Baud Rate generator output signal if test mode is selected in the Power and Test Configuration Register and the DLAB bit (LCR7) is set After Master Reset this pin provides the SOUT function (See SOUT and CFG0 – 4 for further information) BUSY 84 I Busy This pin is set high by the printer when it cannot accept another character It has a nominal 25 kX pull-down resistor attached to it (See WAIT and Table 7-5 for further information) CFG0 – 4 65 66 I Default Configuration These CMOS inputs select 1 of 32 default configurations in which the PC87322VF will power-up (see Table 2-1) An internal pull-down resistor of 30 kX is on each pin Use a 71 73 10 kX resistor to pull these pins to VCC 74 CSOUT 3O Chip Select Output When the associated bit in the Power and Test Configuration Register is set this multi-function pin provides an active signal each time the internal address decoder decodes an address enabled for the PC87322VF (See PWDN and ZWS for further information) CTS12 72 64 I Clear to Send When low this indicates that the MODEM or data set is ready to exchange data The CTS signal is a MODEM status input whose condition the CPU can test by reading bit 4 (CTS) of the MODEM Status Register (MSR) for the appropriate serial channel Bit 4 is the complement of the CTS signal Bit 0 (DCTS) of the MSR indicates whether the CTS input has changed state since the previous reading of the MSR CTS has no effect on the transmitter Note Whenever the DCTS bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled D7–D0 10–17 I O Data Bi-directional data lines to the microprocessor D0 is the LSB and D7 is the MSB These signals all have 24 mA (sink) buffered outputs DACK 5I DMA Acknowledge Active low input to acknowledge the FDC DMA request and enable the RD and WR inputs during a DMA transfer When in PC-AT or Model 30 mode this signal is enabled by bit D3 of the Digital Output Register (DOR) When in PS2 mode DACK is always enabled and bit D3 of the DOR is reserved DACK should be held high during PIO accesses DCD12 77 69 I Data Carrier Detect When low this indicates that the MODEM or data set has detected the data carrier The DCD signal is a MODEM status input whose condition the CPU can test by reading bit 7 (DCD) of the MODEM Status Register (MSR) for the appropriate serial channel Bit 7 is the complement of the DCD signal Bit 3 (DDCD) of the MSR indicates whether the DCD input has changed state since the previous reading of the MSR Note Whenever the DDCD bit of the MSR is set an interrupt is generated if MODEM Status interrupts are enabled DENSEL 48 O Density Select Indicates when a high FDC density data rate (500 kbs or 1 Mbs) or a low density data rate (250 or 300 kbs) has been selected DENSEL is active high for high density (525 drives) when IDENT is high and active low for high density (35 drives) when IDENT is low DENSEL is also programmable via the Mode command (see Section 426) 78 O Density Select This pin provides an additional Density Select in PPM Mode when PNFe0 (See AFD and Table 7-5 for further information) 7 |
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Similar Description - PC87322VF |
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