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PC87383-VS Datasheet(PDF) 5 Page - National Semiconductor (TI) |
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PC87383-VS Datasheet(HTML) 5 Page - National Semiconductor (TI) |
5 / 77 page Table of Contents (Continued) Revision 1.1 5 www.national.com 3.3.2 Floating Module Output ............................................................................................... 25 3.4 INTERNAL ADDRESS DECODING .......................................................................................... 26 3.5 PROTECTION ........................................................................................................................... 26 3.5.1 Multiplexed Pins Configuration Lock ........................................................................... 26 3.5.2 GPIO Ports Configuration Lock ................................................................................... 26 3.5.3 Fast Disable Configuration Lock .................................................................................. 26 3.5.4 Clock Control Lock ...................................................................................................... 26 3.5.5 GPIO Ports Lock .......................................................................................................... 26 3.6 REGISTER TYPE ABBREVIATIONS ........................................................................................ 27 3.7 SUPERI/O CONFIGURATION REGISTERS ............................................................................. 27 3.7.1 SuperI/O ID Register (SID) .......................................................................................... 27 3.7.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 28 3.7.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 29 3.7.4 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 30 3.7.5 SuperI/O Revision ID Register (SRID) ........................................................................ 30 3.7.6 Clock Generator Control Register (CLOCKCF) ........................................................... 31 3.8 PARALLEL PORT (PP) CONFIGURATION .............................................................................. 32 3.8.1 General Description ..................................................................................................... 32 3.8.2 Logical Device 1 (PP) Configuration ............................................................................ 32 3.8.3 Parallel Port Configuration Register ............................................................................ 33 3.9 INFRARED CONFIGURATION ................................................................................................. 34 3.9.1 Logical Device 2 (IR) Configuration ............................................................................. 34 3.9.2 Infrared Configuration Register ................................................................................... 34 3.10 SERIAL PORT 1 CONFIGURATION ......................................................................................... 35 3.10.1 Logical Device 3 (SP1) Configuration .......................................................................... 35 3.10.2 Serial Port 1 Configuration Register ............................................................................ 35 3.11 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 36 3.11.1 General Description ..................................................................................................... 36 3.11.2 Implementation ............................................................................................................36 3.11.3 Logical Device 7 (GPIO) Configuration ....................................................................... 37 3.11.4 GPIO Pin Select Register (GPSEL) ............................................................................. 38 3.11.5 GPIO Pin Configuration Register (GPCFG) ................................................................ 38 3.11.6 GPIO Event Routing Register (GPEVR) ...................................................................... 40 |
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