12345

6789

S

1110

1

A1 A0

1

A

A

I0.x

A

I1.x

A

I0.x

1

I1.x

P

R/W

ACKNOWLEDGE

FROM SLAVE

SCL

SDA

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

ACKNOWLEDGE

FROM MASTER

NON ACKNOWLEDGE

FROM MASTER

READ FROM PORT 0

DATA INTO PORT 0

READ FROM PORT 1

DATA INTO PORT 1

INT

SW02209

DATA 00

DATA 10

DATA 03

DATA 12

DATA 00

DATA 01

DATA 02

DATA 03

DATA 10

DATA 11

DATA 12

NOTES: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode).

It is assumed that the command byte has previously been set to 00 (read input port port register).

Figure 10.

READ input port register — scenario 2