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PC7410VGSU450N Datasheet(PDF) 10 Page - ATMEL Corporation |
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PC7410VGSU450N Datasheet(HTML) 10 Page - ATMEL Corporation |
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10 / 54 page  10 PC7410 2141D–HIREL–02/04 Figure 3. Overshoot/Undershoot Voltage The PC7410 provides several I/O voltages to support both compatibility with existing systems and migration to future systems. The PC7410 “core” voltage must always be provided at nominal voltage (see Table 4 for actual recommended core voltage). Volt- age to the L2 I/Os and processor interface I/Os are provided through separate sets of supply pins and may be provided at the voltages shown in Table 3. The input voltage threshold for each bus is selected by sampling the state of the voltage select pins at the negation of the signal HRESET. The output voltage will swing from GND to the maxi- mum voltage applied to the OV DD or L2OVDD power pins. Notes: 1. Caution: The input threshold selection must agree with the OV DD/L2OVDD voltages supplied. 2. To select the 2.5V threshold option, L2VSEL/BVSEL should be tied to HRESET so that the two signals change state together. This is the preferred method for selecting this mode operation. 3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used. 4. Default voltage setting if left unconnected (internal pulled-up). Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, the default voltage setting if left unconnected is 2.5V. 5. Parts Rev 1.4 and later only. Previous revisions do not support 3.3V OVDD, having BVSEL = 1 selects the 2.5V threshold. 6. Parts Rev 1.4 and later only. Previous revisions do not support BVSEL = HRESET. 7. NSpec does not support the default OVDD setting of 3.3V. The BVSEL input must be tie either low or HRESET. Table 3. Input Threshold Voltage Setting BVSEL Signal Processor Bus Input Threshold is Relative to: L2VSEL Signal(3) L2 Bus Input Threshold is Relative to: 0(1) 1.8V 0 1.8 HRESET(1)(2) 2.5V HRESET 2.5 1(1)(4)(5) 3.3V(7) 12.5 HRESET(6) 3.3V(7) HRESET Not supported Not to exceed 10% of tSYSCLK (L2)OVDD + 20% (L2)OVDD + 5% (L2)OVDD VIH VIL GND GND - 0.3V GND - 0.7V |
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