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PC7410VGHU500N Datasheet(PDF) 5 Page - ATMEL Corporation

Part # PC7410VGHU500N
Description  PowerPC 7410 RISC Microprocessor Product Specification
Download  54 Pages
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Manufacturer  ATMEL [ATMEL Corporation]
Direct Link  http://www.atmel.com
Logo ATMEL - ATMEL Corporation

PC7410VGHU500N Datasheet(HTML) 5 Page - ATMEL Corporation

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5
PC7410
2141D–HIREL–02/04
Completion of instructions in program order while supporting out-of-order
instruction execution, completion serialization and all instruction flow
changes
Fixed-point Units (FXUs) that Share 32 GPRs for Integer Operands
Fixed-point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical
Fixed-point unit 2 (FXU2)—shift, rotate, arithmetic, logical
Single-cycle arithmetic, shifts, rotates, logical
Multiply and divide support (multi-cycle)
Early out multiply
Three-stage Floating-point Unit and a 32-entry FPR File
Support for IEEE-754 standard single- and double-precision floating-point
arithmetic
Three-cycle latency, one-cycle throughput (single or double precision)
Hardware support for divide
Hardware support for denormalized numbers
Time deterministic non-IEEE mode
System Unit
Executes CR logical instructions and miscellaneous system instructions
Special register transfer instructions
AltiVec Unit
Full 128-bit data paths
Two dispatchable units: vector permute unit and vector ALU unit
Contains its own 32-entry 128-bit vector register file (VRF) with six renames
The vector ALU unit is further sub-divided into the vector simple integer unit
(VSIU), the vector complex integer unit (VCIU) and the vector floating-point
unit (VFPU).
Fully pipelined
Load/Store Unit
One-cycle load or store cache access (byte, half-word, word, double-word)
Two-cycle load latency with one-cycle throughput
Effective address generation
Hits under misses (multiple outstanding misses)
Single-cycle unaligned access within double-word boundary
Alignment, zero padding, sign extend for integer register file
Floating-point internal format conversion (alignment, normalization)
Sequencing for load/store multiples and string operations
Store gathering
Executes the cache and TLB instructions
Big- and little-endian byte addressing supported
Misaligned little-endian supported
Supports FXU, FPU, and AltiVec load/store traffic
Complete support for all four architecture AltiVec DST streams
Level 1 (L1) Cache Structure
32K 32-byte line, 8-way set associative instruction cache (iL1)


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