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SPT774BCS Datasheet(PDF) 4 Page - List of Unclassifed Manufacturers |
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SPT774BCS Datasheet(HTML) 4 Page - List of Unclassifed Manufacturers |
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4 / 12 page  SPT 4 8/1/00 SPT774 ELECTRICAL SPECIFICATIONS TA = TMIN to TMAX, VEE = 0 to +5 V, VDD = +5 V, fS = 117 kHz, fIN = 10 kHz, unless otherwise specified. TEST TEST SPT774C SPT774B PARAMETER CONDITIONS LEVEL MIN TYP MAX MIN TYP MAX UNITS AC ELECTRICAL CHARACTERISTICS4 Convert Mode Timing tDSC STS Delay from CE VI 60 200 60 200 ns tHEC CE Pulse Width VI 50 30 50 30 ns tSSC CS to CE Setup VI 50 20 50 20 ns tHSC CS Low during CE High VI 50 20 50 20 ns tSRC R/C to CE Setup VI 50 0 50 0 ns tHRC R/C Low During CE High VI 50 20 50 20 ns tSAC Ao to CE Setup VI 0 0 ns tHAC Ao Valid During CE High VI 50 20 50 20 ns tC Conversion Time5 12-Bit Cycle VI 7.5 8 7.5 8 µs 8-Bit Cycle VI 5.5 5.9 5.5 5.9 µs Read Mode Timing tDD Access Time from CE VI 75 150 75 150 ns tHD Data Valid After CE Low VI 25 35 25 35 ns tHL Output Float Delay VI 100 150 100 150 ns tSSR CS to CE Setup VI 50 0 50 0 ns tSRR R/C to CE Setup VI 0 0 ns tSAR Ao to CE Setup VI 50 25 50 25 ns tHSR CS Valid After CE Low VI 0 0 ns tHRR R/C High After CE Low VI 0 0 ns tHS STS Delay After Data Valid VI 75 150 375 75 150 375 ns tHAR Ao Valid after CE Low VI 50 50 ns Note 4: Time is measured from 50% level of digital transitions. Note 5: Includes acquisition time. tHEC t SSC t SRC t HSC t HRC t HAC t SAC t DSC High Impedance tC DB11-DB0 STS Ao R/C CE CS Figure 1 - Convert Mode Timing Diagram Figure 2 - Read Mode Timing Diagram t SSR Ao CE CS t HSR t HRR t SRR t SAR t HAR STS DATA VALID t HL HIGH IMPEDANCE DB11-DB0 R/C t HS t HD t DD |
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