AD9804JST datasheet(3/8 Pages) AD

Part #	AD9804JST

Description	Complete 10-Bit 18 MSPS CCD Signal Processor

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Manufacturer	AD [Analog Devices]

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REV. 0

–3–

AD9804

TIMING SPECIFICATIONS

Parameter

Symbol

Min

Typ

Max

Unit

SAMPLE CLOCKS

DATACLK, SHP, SHD Clock Period

tCONV

55.6

ns

DATACLK Hi/Low Pulsewidth

tADC

20

27.7

ns

SHP Pulsewidth

tSHP

10

14

ns

SHD Pulsewidth

tSHD

10

14

ns

CLPDM Pulsewidth

tCDM

410

Pixels

CLPOB Pulsewidth

1

tCOB

210

Pixels

SHP Rising Edge to SHD Falling Edge

tS1

20

27

ns

SHP Rising Edge to SHD Rising Edge

tS2

20

27

ns

Internal Clock Delay

tID

3.0

ns

Inhibited Clock Period

tINH

10

ns

DATA OUTPUTS

Output Delay

tOD

14.5

16

ns

Output Hold Time

tH

6.0

7.6

ns

Pipeline Delay

9

Cycles

SERIAL INTERFACE

Maximum SCK Frequency

fSCLK

10

MHz

SL to SCK Setup Time

tLS

10

ns

SCK to SL Hold Time

tLH

10

ns

SDATA Valid to SCK Rising Edge Setup

tDS

10

ns

SCK Falling Edge to SDATA Valid Hold

tDH

10

ns

SCK Falling Edge to SDATA Valid Read

tDV

10

ns

NOTES

1Minimum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance.

Specifications subject to change without notice

(CL = 20 pF, fCLK = 18 MHz, timing shown in Figures 1 and 2.)

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD9804 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

With

Respect

Parameter

To

Min

Max

Unit

AVDD

AVSS

–0.3

+3.9

V

DVDD

DVSS

–0.3

+3.9

V

DRVDD

DRVSS

–0.3

+3.9

V

Digital Outputs

DRVSS

–0.3

DRVDD + 0.3 V

SHP, SHD, DATACLK

DVSS

–0.3

DVDD + 0.3

V

CLPOB, CLPDM, PBLK DVSS

–0.3

DVDD + 0.3

V

SCK, SL, SDATA

DVSS

–0.3

DVDD + 0.3

V

VRT, VRB, CMLEVEL

AVSS

–0.3

AVDD + 0.3

V

BYP1–4, CCDIN

AVSS

–0.3

AVDD + 0.3

V

Junction Temperature

150

°C

Lead Temperature

300

°C

(10 sec)

ORDERING GUIDE

Temperature

Package

Model

Range

Description

Option

AD9804JST

–20

°C to +85°CThin Plastic

ST-48

Quad Flatpack

(LQFP)

THERMAL CHARACTERISTICS

Thermal Resistance

48-Lead LQFP Package

θJA = 92°C/W

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