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ATMEGA1281 Datasheet(PDF) 7 Page - ATMEL Corporation |
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ATMEGA1281 Datasheet(HTML) 7 Page - ATMEL Corporation |
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7 / 407 page  7 ATmega640/1280/1281/2560/2561 2549A–AVR–03/05 current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running. Por t D also se rve s t h e fu nctio n s of var i ous sp ecia l fea t u r es of th e ATmega640/1280/1281/2560/2561 as listed on page 94. Port E (PE7..PE0) Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running. Por t E also ser v es the fu nctio n s of va r i ou s sp ecia l f e a t ur es of t h e ATmega640/1280/1281/2560/2561 as listed on page 96. Port F (PF7..PF0) Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resis- tors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs. Port F also serves the functions of the JTAG interface. Port G (PG5..PG0) Port G is a 6-bit I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running. Por t G also se rve s t he fu nctio n s of va riou s spe c ial fea t ur es of th e ATmega640/1280/1281/2560/2561 as listed on page 102. Port H (PH7..PH0) Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running. Por t H also se rve s t h e fu nctio n s of var i ous sp ecia l fea t u r es of th e ATmega640/1280/1281/2560/2561 as listed on page 104. Port J (PJ7..PJ0) Port J is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running. Por t J also s e rve s th e fun c tion s of v a rio u s sp ecial fe atu r e s of th e ATmega640/1280/1281/2560/2561 as listed on page 106. Port K (PK7..PK0) Port K serves as analog inputs to the A/D Converter. |
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