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HT82J97E-28SOP-A Datasheet(PDF) 6 Page - Holtek Semiconductor Inc |
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HT82J97E-28SOP-A Datasheet(HTML) 6 Page - Holtek Semiconductor Inc |
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6 / 46 page  HT82J97E Rev. 1.30 6 May 10, 2004 Stack Register - STACK This is a special part of the memory which is used to save the contents of the program counter (PC) only. The stack is organized into 8 levels and is neither part of the data nor part of the program space, and is neither read- able nor writeable. The activated level is indexed by the stack pointer (SP) and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the program counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction (RET or RETI), the pro- gram counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a non-masked interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the stack pointer is decremented (by RET or RETI), the interrupt will be serviced. This feature prevents stack overflow al- lowing the programmer to use the structure more easily. In a similar case, if the stack is full and a ²CALL² is sub- sequently executed, stack overflow occurs and the first entry will be lost (only the most recent 8 return ad- dresses are stored). Data Memory - RAM for Bank 0 The data memory is designed with 96 ´8 bits. The data memory is divided into two functional groups: special function registers and general purpose data memory (96 ´8). Most are read/write, but some are read only. The special function registers include the indirect ad- dressing registers (R0;00H, R1;02H), Bank register (BP, 04H), PWM1 duty register (0DH), PWM2 duty regis- ter(0EH), Timer/Event Counter higher order byte regis- ter (TMRH;0FH), Timer/Event Counter lower order byte register (TMRL;10H), Timer/Event Counter control reg- ister (TMRC;11H), program counter lower-order byte register (PCL;06H), memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointers (TBLP;07H, TBHP;1FH), table higher-order byte register (TBLH;08H), status register (STATUS;0AH), interrupt control register (INTC;0BH), Watchdog Timer option setting register (WDTS;09H), I/O registers (PA;12H, PB;14H, PC;16H), PWM Base Period Register (18H), I/O control registers (PAC;13H, PBC;15H, PCC;17H). USB/PS2 status and control reg- ister (USC;1AH), USB endpoint interrupt status register (USR;1BH), system clock control register (SCC;1CH). A/D converter status and control register (ADSC;1DH) and A/D converter result register (ADR;1EH). The re- maining space before the 20H is reserved for future ex- panded usage and reading these locations will get ²00H². The general purpose data memory, addressed from 20H to 7FH, is used for data and control informa- tion under instruction commands. All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by ²SET [m].i² and ²CLR [m].i². They are also indirectly accessible through memory pointer registers (MP0 or MP1). 0 0 H 0 1 H 0 2 H 0 3 H 0 4 H 0 5 H 0 6 H 0 7 H 0 8 H 0 9 H 0 A H 0 B H 0 C H 0 D H 0 E H 0 F H 1 0 H 1 1 H 1 2 H 1 3 H 1 4 H 1 5 H 1 6 H 1 7 H 1 8 H G e n e r a l P u r p o s e D A T A M E M O R Y ( 9 6 B y t e s ) 1 A H 1 B H 1 C H 1 D H 1 E H 1 F H 7 F H 2 0 H I n d i r e c t A d d r e s s i n g R e g i s t e r 0 M P 0 I n d i r e c t A d d r e s s i n g R e g i s t e r 1 M P 1 B P A C C P C L T B L P T B L H W D T S S T A T U S I N T C P W M 1 D u t y R e g i s t e r P W M 2 D u t y R e g i s t e r T M R H T M R L T M R C P A P A C P B P B C P C P C C P W M B a s e P e r i o d R e g i s t e r ( P D ) U S C U S R S C C A D S C A D R T B H P B a n k 0 1 9 H Bank 0 RAM Mapping |
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