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CXK79M36C162GB-5 Datasheet(PDF) 3 Page - Sony Corporation |
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CXK79M36C162GB-5 Datasheet(HTML) 3 Page - Sony Corporation |
3 / 25 page SONY® ΣRAM Preliminary 18Mb 1x2Lp, HSTL, rev 1.1 3 / 25 November 8, 2002 CXK79M36C162GB Pin Description Symbol Type Quantity Description A Input 17 Address Inputs - Registered on the rising edge of CK. A1 Input 1 Address Input 1 - Registered on the rising edge of CK. Initializes burst counter. DQ I/O 36 Data Inputs / Outputs - Registered on the rising and falling edges of CK during write operations. Driven from the rising and falling edges of CK during read operations. CK, CK Input 2 Differential Input Clocks CQ1, CQ1 CQ2, CQ2 Output 4 Output Clocks E1 Input 1 Chip Enable Control Input - Registered on the rising edge of CK. E1 = 0 enables the device to accept read and write commands. E1 = 1 disables the device. See the Clock Truth Table section for further information. E2, E3 Input 2 Programmable Chip Enable Control Inputs - Registered on the rising edge of CK. See the Clock Truth Table and Depth Expansion sections for further information. EP2, EP3 Input 2 Programmable Chip Enable Active-Level Select Inputs - These pins must be tied “high” or “low” at power-up. See the Clock Truth Table and Depth Expansion sec- tions for further information. ADV Input 1 Address Advance Control Input - Registered on the rising edge of CK. ADV = 0 loads a new address and begins a new operation when the device is enabled. ADV = 1 increments the address and continues the previous operation when the device is enabled. See the Clock Truth Table section for further information. W Input 1 Write Enable Control Input - Registered on the rising edge of CK. W = 0 specifies a write operation when ADV = 0 and the device is enabled. W = 1 specifies a read operation when ADV = 0 and the device is enabled. See the Clock Truth Table section for further information. ZQ Input 1 Output Impedance Control Resistor Input - This pin must be tied to VSS through an external resistor RQ at power-up. Output driver impedance is set to one-fifth the value of RQ, nominally. See the Output Driver Impedance Control section for further information. VDD 14 1.8V Core Power Supply - Core supply voltage. VDDQ 24 Output Power Supply - Output buffer supply voltage. VREF 4 Input Reference Voltage - Input buffer threshold voltage. VSS 30 Ground TCK Input 1 JTAG Clock TMS Input 1 JTAG Mode Select - Weakly pulled “high” internally. TDI Input 1 JTAG Data In - Weakly pulled “high” internally. TDO Output 1 JTAG Data Out MCL *Input* 10 Must Connect “Low” - May not be actual input pins. MCH *Input* 3 Must Connect “High” - May not be actual input pins. NC 52 No Connect - These pins are true no-connects, i.e. there is no internal chip connection to these pins. They can be left unconnected or tied directly to VSS. |
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