MAX1419 datasheet(3/18 Pages) MAXIM

Part #	MAX1419

Description	15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications

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Manufacturer	MAXIM [Maxim Integrated Products]

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15-Bit, 100Msps ADC with -77.7dBFS

Noise Floor for Baseband Applications

_______________________________________________________________________________________

3

ELECTRICAL CHARACTERISTICS (continued)

(AVCC = 5V, DVCC = DRVCC = 2.5V, GND = 0, INP and INN driven differentially with -1dBFS, CLKP and CLKN driven differentially

with a 2VP-P sinusoidal input signal, CL = 5pF at digital outputs, fCLK = 100MHz, TA = TMIN to TMAX, unless otherwise noted. Typical

values are at TA = +25°C, unless otherwise noted.

≥+25°C guaranteed by production test, <+25°C guaranteed by design and char-

acterization.)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

fIN = 5MHz at -1dBFS

75.3

fIN = 15MHz at -1dBFS

72.1

75.1

Signal-to-Noise

Ratio (Note 1)

SNR

fIN = 35MHz at -1dBFS

74.8

dB

fIN = 5MHz at -1dBFS

75.0

fIN = 15MHz at -1dBFS

71.7

74.9

Signal-to-Noise

and Distortion

(Note 1)

SINAD

fIN = 35MHz at -1dBFS

71.1

dB

fIN = 5MHz at -1dBFS

90.0

fIN = 15MHz at -1dBFS

84.0

90.0

Spurious-Free Dynamic Range

(HD2 and HD3)

(Note 1)

SFDR1

fIN = 35MHz at -1dBFS

74.0

dBc

fIN = 5MHz at -1dBFS

96.0

fIN = 15MHz at -1dBFS

85.0

94.0

Spurious-Free Dynamic Range

(HD4 and Higher)

(Note 1)

SFDR2

fIN = 35MHz at -1dBFS

92.0

dBc

Two-Tone Intermodulation

Distortion

TTIMD

fIN1 = 10MHz at -7dBFS,

fIN2 = 15MHz at -7dBFS

-85

dBc

Two-Tone Spurious-Free

Dynamic Range

SFDRTT

fIN1 = 10MHz at -10dBFS < fIN1 < -100dBFS,

fIN2 = 15MHz at -10dBFS < fIN2 < -100dBFS

-100

dBFS

DIGITAL OUTPUTS (D0–D14, DAV, DOR)

Digital Output-Voltage Low

VOL

0.5

V

Digital Output-Voltage High

VOH

DRVCC

- 0.5

V

TIMING CHARACTERISTICS (DVCC = DRVCC = 2.5V)

CLKP/CLKN Duty Cycle

Duty Cycle

50

±5

%

Effective Aperture Delay

tAD

230

ps

Output Data Delay

tDAT

(Note 3)

3.0

4.5

7.5

ns

Data Valid Delay

tDAV

(Note 3)

5.3

6.5

8.7

ns

Pipeline Latency

tLATENCY

(Note 3)

3

Clock

cycles

CLKP Rising Edge to DATA Not

Valid

tDNV

(Note 3)

2.6

3.8

5.7

ns

CLKP Rising Edge to DATA Valid

(guaranteed)

tDGV

(Note 3)

3.4

5.2

8.6

ns

DATA Setup Time (Before DAV

Rising Edge)

tSETUP

(Note 3)

tCLKP

- 0.5

tCLKP

+ 1.3

tCLKP +

2.4

ns

DATA Hold Time (After DAV

Rising Edge)

tHOLD

(Note 3)

tCLKN -

3.6

tCLKN -

2.8

tCLKN -

2.0

ns

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