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MP7643AS Datasheet(PDF) 6 Page - Exar Corporation |
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MP7643AS Datasheet(HTML) 6 Page - Exar Corporation |
6 / 12 page MP7643 6 Rev. 1.00 Figure 1. Timing Diagram tAS tAH tDS tDH 1/2 LSB 1/2 LSB A1, A0 DB0 to DB7 LD VOUT tLD tSD 2-4 Decoder A0, A1 LD To DAC1 Latch Enable To DAC2 Latch Enable To DAC3 Latch Enable To DAC4 Latch Enable Figure 2. Input Control Logic (Simplified) Block Diagram L L L DAC1 Transparent ↑ L L DAC1 Latched L L H DAC2 Transparent ↑ L H DAC2 Latched L H L DAC3 Transparent ↑ H L DAC3 Latched L H H DAC4 Transparent ↑ H H DAC4 Latched H X X No Operation LD A1 A0 Operation Table 1. Truth Table D7 D6 D5 D4 D3 D2 D1 D0 MSB LSB DAC Output Voltage VOi = VREFN + (VRi – AGND) ( ) D 256 0000 0 0 00 ( 1 ) 256 1111 1 1 10 1111 1 1 11 000 Table 2. DAC Transfer Function Analog Output vs. Digital Code (With VREF Shorted to INV) 00 00 1 (VRi – VREFN)+ VREFN () 256 (VRi – VREFN)+ VREFN () 256 (VRi – VREFN)+ VREFN 255 254 VREFN Note: These outputs must be ratioed up for gain in the output amplifier. |
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