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PRELIMINARY
CYV15G0404RB
Document #: 38-02102 Rev. **
Page 3 of 26
Reclocking Deserializer Path Block Diagram
INA1+
INA1–
INA2+
INA2–
INSELA
Clock &
Data
Recovery
PLL
LFIA
10
RXDA[9:0]
Receive
Signal
Monitor
RXCLKA+
RXCLKA–
÷2
RXPLLPDA
SPDSELA
ULCA
RXRATEA
10
10
RXBISTA[1:0]
LDTDEN
SDASEL[2..1]A[1:0]
ROUTA1+
ROUTA1–
ROUTA2+
ROUTA2–
ROE[2..1]A
TRGCLKA
x2
TRGRATEA
BISTSTA
Character-Rate Clock A
Reclocker
RECLKOA
Recovered Character Clock
Recovered Serial Data
REPDOA
Clock Multiplier A
Output PLL
ROE[2..1]A
INB1+
INB1–
INB2+
INB2–
INSELB
Clock &
Data
Recovery
PLL
LFIB
10
RXDB[9:0]
Receive
Signal
Monitor
RXCLKB+
RXCLKB–
÷2
RXPLLPDB
SPDSELB
ULCB
RXRATEB
10
10
RXBISTB[1:0]
LDTDEN
SDASEL[2..1]B[1:0]
ROUTB1+
ROUTB1–
ROUTB2+
ROUTB2–
ROE[2..1]B
TRGCLKB
x2
TRGRATEB
BISTSTB
Character-Rate Clock B
Reclocker
RECLKOB
Recovered Character Clock
Recovered Serial Data
REPDOB
Clock Multiplier B
Output PLL
ROE[2..1]B
=
Internal Signal
JTAG
Boundary
Scan
Controller
TDO
TMS
TCLK
TDI
RESET
TRST
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