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MP3274 Datasheet(PDF) 10 Page - Exar Corporation |
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MP3274 Datasheet(HTML) 10 Page - Exar Corporation |
10 / 16 page MP3274 10 Rev. 4.00 Table 4. Serial Data Output Mode Timing ( See Figure 6.) 25 °C Tmin to Tmax Limits Comments/Test Conditions STS low to SDO (DB11) Valid, t20 50 50 ns max Load Ckt 4 of Figure 3. RD = 0 Minimum clock high pulse width t21 50 80 ns max SDC low to data valid delay t22 150 ns 200 ns max Load ckt of Figure 3., CL = 20pF 200 ns 250 ns max Load ckt of Figure 3., CL = 100pF Serial Data Output Timing Time Interval Note 1: If RD = 1, data outputs remain high impedance. It is recommended that RD will not change during a conver- sion in order to reduce noise. It is further recommended that RD = 1 during conversion to reject any noise present on the data bus. Table 5. Logic Truth Table – Serial Data Output Mode CS WR RD ADEN Data STL STS Comments 1 X X X X –– 0 0 X No Operation 0 ↓ X 1 X Hi-Z 0 0 X Serial mode enabled (1) 00 ↓ 1 0 Hi-Z 0 0 X No operation if ADEN = 0 00 ↓ 1 1 Hi-Z ↑ 0 X Input MUX channel selected, STL set on falling edge of WR 0 0 0 1 X Hi-Z 1 0 X MUX select disabled 00 ↑ 1 X Hi-Z 0 ↑ X Start convert on WR rising edge 0 0 1 1 X Hi-Z ↓↑ X Start convert on STL falling edge 0 0 1 1 X Hi-Z 0 ↓ X STS goes low at end of conversion PXS ADC Channel Select and Start Convert DB0/SDC 00 1 ↓ X –– 0 0 1 Serial output (DB11/SDO) and serial clock input (DB0/SDC) enabled 00 X X X MSB (DB11) 0 0 1 MSB data available at DB11/SDO 0 0 X 0 X DB10 0 0 ↓ Next significant bit shifted out to DB11/SDO 0 0 X 0 X DB10 0 0 0 No Operation 0 0 X 0 X DB10 0 0 ↑ No Operation 0 0 X 0 X DB9 0 0 ↓ Next significant bit shifted out to DB11/SDO 00 X ↑ X Hi-Z 0 0 X Data outputs/SDC input disabled 0 X 1 X X Hi-Z 0 1 X Data outputs/RD disabled when STS = 1 0 X 0 0 Hi-Z 0 ↑ 1 STL, MUX select disabled when ADEN = 0 00 0 X MSB (DB11) 0 ↓ 1 New data appears at DB11/SDO on falling edge of STS Read ADC Data ( See Table 4. and Figure 6.) Table 6. Key Output Codes vs. Input Voltage (2’s Complement Code) 2’s Complement Output Code (Hexidecimal) Ideal Transition Voltage +FS – 1 1/2 LSB 0 V +1/2 LSB 0 V –1/2 LSB –FS +1/2 LSB 0111 0000 1111 1000 1111 0000 1111 0000 1110 (7fe) to 0000 (000) to 1111 (fff) to 0000(800) to 0111 0000 0000 1000 1111 0000 0000 0000 1111 (7ff) 0001 (001) 0000 (000) 0001 (801) |
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