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ZL30109QDG Datasheet(PDF) 7 Page - Zarlink Semiconductor Inc |
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ZL30109QDG Datasheet(HTML) 7 Page - Zarlink Semiconductor Inc |
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7 / 36 page  ZL30109 Data Sheet 7 Zarlink Semiconductor Inc. 19 RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300 ns after the power supply pins have reached the minimum supply voltage. When the RST pin goes high, the device will transition into a Reset state for 3 ms. In the Reset state all outputs will be forced into high impedance. 20 OSCo Oscillator Master Clock (Output). For crystal operation, a 20 MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clock oscillator operation, this pin must be left unconnected. 21 OSCi Oscillator Master Clock (Input). For crystal operation, a 20 MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to a clock source. 22 IC Internal Connection. Leave unconnected. 23 GND Ground. 0V. 24 NC No internal bonding Connection. Leave unconnected. 25 VDD Positive Supply Voltage. +3.3 VDC nominal. 26 OUT_SEL Output Selection (Input).This input selects the signals on the combined output clock and frame pulse pins, see Table 3 on page 17. 27 IC Internal Connection. Connect this pin to ground. 28 IC Internal Connection. Connect this pin to ground. 29 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal. 30 NC No internal bonding Connection. Leave unconnected. 31 NC No internal bonding Connection. Leave unconnected. 32 C1.5o Clock 1.544 MHz (Output). This output is used in DS1 applications. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. 33 AGND Analog Ground. 0 V 34 AGND Analog Ground. 0 V 35 AVCORE Positive Analog Supply Voltage. +1.8 VDC nominal. 36 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal. 37 AVDD Positive Analog Supply Voltage. +3.3 VDC nominal. 38 F2ko Multi Frame Pulse (Output). This is a 2 kHz 51 ns active high framing pulse, which marks the beginning of a multi frame. This clock output pad includes a Schmitt input which serves as a PLL feedback path; proper transmission-line termination should be applied to maintain reflections below Schmitt trigger levels. Pin Description (continued) Pin # Name Description |
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